CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18
Functional Overview
The CY7C1392CV18, CY7C1992CV18, CY7C1393CV18, and CY7C1394CV18 are synchronous pipelined Burst SRAMs equipped with a
Accesses are initiated on the rising edge of the positive input clock (K). All synchronous input timing is referenced from the rising edge of the input clocks (K and K) and all output timing is referenced to the rising edge of the output clocks (C/C, or K/K when in single clock mode).
All synchronous data inputs (D[x:0]) pass through input registers controlled by the rising edge of the input clocks (K and K). All synchronous data outputs (Q[x:0]) pass through output registers controlled by the rising edge of the output clocks (C/C, or K/K when in
All synchronous control (R/W, LD, BWS[0:X]) inputs pass through input registers controlled by the rising edge of the input clock (K).
CY7C1393CV18 is described in the following sections. The same basic descriptions apply to CY7C1392CV18, CY7C1992CV18, and CY7C1394CV18.
Read Operations
The CY7C1393CV18 is organized internally as two arrays of 512K x 18. Accesses are completed in a burst of two sequential
The CY7C1393CV18 first completes the pending read transac- tions, when read access is deselected. Synchronous internal circuitry automatically
Write Operations
Write operations are initiated by asserting R/W LOW and LD LOW at the rising edge of the positive input clock (K). The address presented to address inputs is stored in the write address register. On the following K clock rise the data presented to D[17:0] is latched and stored into the
bits of data can be transferred into the device on every rising edge of the input clocks (K and K).
When Write access is deselected, the device ignores all inputs after the pending write operations are completed.
Byte Write Operations
Byte write operations are supported by the CY7C1393CV18. A write operation is initiated as described in the Write Operations section. The bytes that are written are determined by BWS0 and BWS1, which are sampled with each set of
Single Clock Mode
The CY7C1393CV18 can be used with a single clock that controls both the input and output registers. In this mode the device recognizes only a single pair of input clocks (K and K) that control both the input and output registers. This operation is identical to the operation if the device had zero skew between the K/K and C/C clocks. All timing parameters remain the same in this mode. To use this mode of operation, tie C and C HIGH at power on. This function is a strap option and not alterable during device operation.
DDR Operation
The CY7C1393CV18 enables
If a read occurs after a write cycle, address and data for the write are stored in registers. The write information must be stored because the SRAM cannot perform the last word write to the array without conflicting with the read. The data stays in this register until the next write cycle occurs. On the first write cycle after the read(s), the stored data from the earlier write is written into the SRAM array. This is called a posted write.
Depth Expansion
Depth expansion requires replicating the LD control signal for each bank. All other control signals can be common between banks as appropriate.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to enable the SRAM to adjust its output driver impedance. The value of RQ must be 5x the value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a tolerance of ±15% is between 175Ω and 350Ω, with VDDQ = 1.5V. The output impedance is adjusted every 1024 cycles at power up to account for drifts in supply voltage and temperature.
Echo Clocks
Echo clocks are provided on the
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