167 | Cypress CY7C1992CV18, CY7C1393CV18, CY7C1394CV18, CY7C1392CV18

CY7C1392CV18, CY7C1992CV18

CY7C1393CV18, CY7C1394CV18

Ordering Information (continued)

Not all of the speed, package, and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered.

Speed	Ordering Code	Package	Package Type	Operating
(MHz)	Ordering Code	Diagram	Package Type	Range
167	CY7C1392CV18-167BZC	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)	Commercial

	CY7C1992CV18-167BZC

	CY7C1393CV18-167BZC

	CY7C1394CV18-167BZC

	CY7C1392CV18-167BZXC	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

	CY7C1992CV18-167BZXC

	CY7C1393CV18-167BZXC

	CY7C1394CV18-167BZXC

	CY7C1392CV18-167BZI	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)	Industrial

	CY7C1992CV18-167BZI

	CY7C1393CV18-167BZI

	CY7C1394CV18-167BZI

	CY7C1392CV18-167BZXI	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

	CY7C1992CV18-167BZXI

	CY7C1393CV18-167BZXI

	CY7C1394CV18-167BZXI

Document #: 001-07162 Rev. *C

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Cypress CY7C1992CV18, CY7C1393CV18, CY7C1394CV18, CY7C1392CV18 manual 167

Contents

Features ConfigurationsFunctional Description Selection Guide CLK Logic Block Diagram CY7C1392CV18Doff Logic Block Diagram CY7C1393CV18 Logic Block Diagram CY7C1394CV18512K Array Gen Read Data Reg Control Pin Configuration Ball Fbga 13 x 15 x 1.4 mm PinoutCY7C1392CV18 2M x CY7C1992CV18 2M x CY7C1393CV18 1M x CY7C1394CV18 512K x Pin Name Pin Description Pin DefinitionsSynchronous Read/Write input. When Power supply inputs to the core of the device Power supply inputs for the outputs of the deviceIs referenced with respect to TDO for Jtag Functional Overview Application Example Shows four DDR-II SIO used in an application Truth Table Write Cycle DescriptionsOperation Comments Write cycle description table for CY7C1992CV18 follows Write cycle description table for CY7C1394CV18 followsDevice Into the device. D359 remains unaltered Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram State diagram for the TAP controller follows TAP Controller Block Diagram TAP Electrical Characteristics TAP AC Switching Characteristics TAP Timing and Test Conditions Identification Register Definitions Scan Register SizesInstruction Codes Register Name Bit Size Boundary Scan Order Bit # Bump ID Power Up Sequence Power Up Sequence in DDR-II SramDLL Constraints DC Electrical Characteristics Electrical CharacteristicsMaximum Ratings Input High Voltage Vref + AC Electrical CharacteristicsInput LOW Voltage Vref Document # 001-07162 Rev. *C Capacitance Thermal ResistanceParameter Description Test Conditions Max Unit Parameter Description Test Conditions Fbga Unit Switching Characteristics Parameter Min MaxHigh LOW Parameter Min Max Output Times DLL Timing Switching Waveforms Burst Ordering Information 250 167 Package Diagram Ball Fbga 13 x 15 x 1.4 mm Worldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal InformationDocument History