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Cypress CY7C1392CV18, CY7C1393CV18, CY7C1394CV18, CY7C1992CV18 Ordering Information

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CY7C1392CV18, CY7C1992CV18

CY7C1393CV18, CY7C1394CV18

Document #: 001-07162 Rev. *C Page 28 of 30

167 CY7C1392CV18-167BZC 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Commercial

CY7C1992CV18-167BZC

CY7C1393CV18-167BZC

CY7C1394CV18-167BZC

CY7C1392CV18-167BZXC 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

CY7C1992CV18-167BZXC

CY7C1393CV18-167BZXC

CY7C1394CV18-167BZXC

CY7C1392CV18-167BZI 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Industrial

CY7C1992CV18-167BZI

CY7C1393CV18-167BZI

CY7C1394CV18-167BZI

CY7C1392CV18-167BZXI 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

CY7C1992CV18-167BZXI

CY7C1393CV18-167BZXI

CY7C1394CV18-167BZXI

Ordering Information (continued)

Not all of the speed, package, and temperature ranges are available. Please contact your local sales representative or

visit www.cypress.com for actual products offered.

Speed

(MHz) Ordering Code Package

Diagram Package Type Operating

Range

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Contents

Main 18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 Features Configurations Functional Description CY7C1392CV18, CY7C1992CV18 Logic Block Diagram (CY7C1392CV18) Logic Block Diagram (CY7C1992CV18) A CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 Logic Block Diagram (CY7C1393CV18) Logic Block Diagram (CY7C1394CV18) A CY7C1393CV18, CY7C1394CV18 Pin Configuration 165-Ball FBGA (13 x 15 x 1.4 mm) Pinout Pin Configuration 165-Ball FBGA (13 x 15 x 1.4 mm) Pinout Pin Definitions CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 Pin Definitions CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 Functional Overview Read Operations Write Operations Byte Write Operations CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 DLL Application Example Truth Table Write Cycle Descriptions Page IEEE 1149.1 Serial Boundary Scan (JTAG) Disabling the JTAG Feature Test Access PortTest Clock Test Mode Select (TMS) Test D ata- In (T DI) CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 TAP Controller State Diagram TAP Controller Block Diagram TAP Electrical Characteristics TAP AC Switching Characteristics TAP Timing and Test Conditions Identification Register Definitions Scan Register Sizes Instruction Codes CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 Boundary Scan Order CY7C1392CV18, CY7C1992CV18 Power Up Sequence in DDR-II SRAM VV Power Up Sequence DLL Constraints Maximum Ratings Operating Range Electrical Characteristics DC Electrical Characteristics AC Electrical Characteristics Electrical Characteristics DC Electrical Characteristics Capacitance Thermal Resistance Page Switching Characteristics Switching Waveforms Page Page Ordering Information Document #: 001-07162 Rev. *C Page 29 of 30 Package Diagram [+] Feedback SOLDERPAD TYPE : NON-SOLDER MASK DEFINED (NSMD) 1.40MAX. Figure 6. 165-Ball FBGA (13 x 15 x 1.4 mm), 51-85180 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC Solutions Document History Page