Accumulator Register, Index Register, Bit 70 X | Cypress CY7C602xx

9.1.1 Accumulator Register

CY7C601xx, CY7C602xx

9.1.1 Accumulator Register

Table 9-2. CPU Accumulator Register (CPU_A)

Bit #	7	6	5	4	3	2	1	0
Field				CPU Accumulator [7:0]
Read/Write	–	–	–	–	–	–	–	–
Default	0	0	0	0	0	0	0	0

Bit [7:0]: CPU Accumulator [7:0]

8-bit data value holds the result of any logical or arithmetic instruction that uses a source addressing mode.

9.1.2 Index Register

Table 9-3. CPU X Register (CPU_X)

Bit #	7	6	5	4		3	2	1	0
Field					X [7:0]
Read/Write	–	–	–	–		–	–	–	–
Default	0	0	0	0		0	0	0	0

Bit [7:0]: X [7:0]

8-bit data value holds an index for any instruction that uses an indexed addressing mode.

9.1.3 Stack Pointer Register

Table 9-4. CPU Stack Pointer Register (CPU_SP)

Bit #	7	6	5	4	3	2	1	0
Field				Stack Pointer [7:0]
Read/Write	–	–	–	–	–	–	–	–
Default	0	0	0	0	0	0	0	0

Bit [7:0]: Stack Pointer [7:0]

8-bit data value holds a pointer to the current top-of-stack.

9.1.4 CPU Program Counter High Register

Table 9-5. CPU Program Counter High Register (CPU_PCH)

Bit #	7	6	5	4	3	2	1	0
Field				Program Counter [15:8]
Read/Write	–	–	–	–	–	–	–	–
Default	0	0	0	0	0	0	0	0

Bit [7:0]: Program Counter [15:8]

8-bit data value holds the higher byte of the program counter.

9.1.5 CPU Program Counter Low Register

Table 9-6. CPU Program Counter Low Register (CPU_PCL)

Bit #	7	6	5	4	3	2	1	0
Field				Program Counter [7:0]
Read/Write	–	–	–	–	–	–	–	–
Default	0	0	0	0	0	0	0	0

Bit [7:0]: Program Counter [7:0]

8-bit data value holds the lower byte of the program counter.

Document 38-16016 Rev. *E

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Cypress CY7C602xx, CY7C601xx manual 2. CPU Accumulator Register CPUA, Index Register, 3. CPU X Register CPUX, Bit 70 X

Contents

2. Logic Block Diagram 1. FeaturesCY7C601xx, CY7C602xx Cypress Semiconductor Corporation 3. Applications 4. Introduction5. Conventions 6. Pinouts Figure 6-1. Package Configurations Top ViewCY7C60223 24-Pin PDIP 6.1 Pin Assignments CY7C601xx, CY7C602xxTable 6-1. Pin Assignments Name Table 6-1. Pin Assignments continued 7. Register Summary DefaultTable 7-1. enCoRe II LV Register Summary Addr Table 7-1. enCoRe II LV Register Summary continued 9. CPU Registers 8. CPU Architecture9.1 Flags Register Table 8-1. CPU Registers and Register Name Table 9-2. CPU Accumulator Register CPUA 9.1.1 Accumulator Register9.1.2 Index Register Table 9-3. CPU X Register CPUX 9.2.1 Source Immediate 9.2 Addressing ModesTable 9-7. Source Immediate Opcode Table 9-11. Destination Indexed 9.2.5 Destination IndexedExample 9.2.6 Destination Direct Source Immediate 9.2.9 Source Indirect Post Increment 10. Instruction Set SummaryTable 9-15. Source Indirect Post Increment 9.2.10 Destination Indirect Post Increment Cycles 11.1 Flash Program Memory Organization 11. Memory OrganizationFigure 11-1. Program Memory Space with Interrupt Vector Table 0x1FFF 11.3 Flash 11.2 Data Memory Organization11.4 SROM Figure 11-2. Data Memory Organization 11.5 SROM Function Descriptions 11.5.1 SWBootReset FunctionTable 11-2. SROM Function Parameters Variable Name 11.5.3 WriteBlock Function SettingsTable 11-5. WriteBlock Parameters 11.5.4 EraseBlock Function 11.5.6 EraseAll Function Table 11-8. ProtectBlock Parameters11.5.7 TableRead Function Table 11-10. Table Read Parameters Page 19 of 11.6 SROM Table Read Description eg ti 12. Clocking Table 12-1. Oscillator Trim Values vs. Voltage Settings12.1 Trim Values for the IOSCTR Register Gain value for the register at location 0x38 3.3V = 12.2.1 CPU Clock 12.2 Clock Architecture Description Table 12-2. CPU Clock Configuration CPUCLKCR 0x30 R/W Figure 12-1. CPU Clock Block DiagramBit 71 Reserved Table 12-3. OSC Control 0 OSCCR0 0x1E0 R/W Sleep Timer Clock Sleep TimerCPU when Internal Table 12-3. OSC Control 0 OSCCR0 0x1E0 R/W continued Table 12-4. Clock IO Configuration CLKIOCR 0x32 R/W 12.2.2 Interval Timer Clock ITMRCLKBit 75 Reserved Figure 12-2. Programmable Interval Timer Block Diagram 12.2.3 Timer Capture Clock TCAPCLKFigure 12-3. Timer Capture Block Diagram Page 27 of Table 12-5. Timer Clock Configuration TMRCLKCR 0x31 R/W 12.2.4 Internal Clock Trim XGM SettingTable 12-6. IOSC Trim IOSCTR 0x34 R/W Bit 40 Gain 12.3 CPU Clock During Sleep Mode 12.2.6 LPOSC TrimTable 12-8. LPOSC Trim LPOSCTR 0x36 R/W Table 13-1. System Status and Control Register CPUSCR 0xFF R/W 13. ResetBit 7 GIES Bit 5 WDRS 13.2 Watchdog Timer Reset 13.1 Power On ResetTable 13-2. Reset Watchdog Timer RESWDT 0xE3 W 14. Sleep Mode 14.1 Sleep Sequence 14.1.1 Low Power in Sleep ModeCPUCLK IOW SLEEP BRQ BRA PD Figure 14-1. Sleep Timing Figure 14-2. Wakeup Timing 14.2 Wakeup Sequence Table 15-1. Low Voltage Control Register LVDCR 0x1E3 R/W 15. Low Voltage Detect ControlBit 76 Reserved Bit 54 PORLEV10 Bit 20 VM20 15.2 ECO Trim Register 15.1 POR Compare StateTable 15-2. Voltage Monitor Comparators Register VLTCMP 0x1E4 R Bit 72 Reserved Bit 1 LVD 16.1 Port Data Registers 16. General Purpose IO Ports16.1.1 P0 Data Table 16-1. P0 Data Register P0DATA0x00 R/W 16.2.1 Int Enable 16.2 GPIO Port Configuration16.1.3 P2 Data Table 16-3. P2 Data Register P2DATA 0x02 R/W 16.2.6 Pull Up Enable 16.2.7 Output EnableFigure 16-1. GPIO Block Diagram 16.2.9 P0.0/CLKIN Configuration 16.2.10 P0.1/CLKOUT Configuration Table 16-7. P0.1/CLKOUT Configuration P01CR 0x06 R/W16.2.11 P0.2/INT0-P0.4/INT2 Configuration 16.2.13 P0.7 Configuration 16.2.12 P0.5/TIO0-P0.6/TIO1 ConfigurationTable 16-10. P0.7 Configuration P07CR 0x0C R/W 16.2.14 P1.0 Configuration Table 16-12. P1.1 Configuration P11CR 0x0E R/W 16.2.15 P1.1 Configuration16.2.16 P1.2 Configuration Table 16-13. P1.2 Configuration P12CR 0x0F R/W Table 16-15. P1.4-P1.6 Configuration P14CR-P16CR 0x11-0x13 R/W 16.2.18 P1.4-P1.6 Configuration SCLK, SMOSI, SMISO16.2.19 P1.7 Configuration Table 16-16. P1.7 Configuration P17CR 0x14 R/W Table 16-18. P3 Configuration P3CR 0x16 R/W 16.2.21 P3 Configuration16.2.22 P4 Configuration Table 16-19. P4 Configuration P4CR 0x17 R/W 17. Serial Peripheral Interface SPI Figure 17-1. SPI Block Diagram Table 17-2. SPI Configure Register SPICR 0x3D R/W 17.2 SPI Configure Register17.1 SPI Data Register Table 17-1. SPI Data Register SPIDATA 0x3C R/W Diagram Table 17-3. SPI Mode Timing vs. LSB First, CPOL, and CPHACPHA CPOL 17.3 SPI Interface Pins 18. Timer RegistersFigure 18-1. 16-Bit Free Running Counter Block Diagram Table 18-1. Free Running Timer Low Order Byte FRTMRL 0x20 R/W Figure 18-2. Time Capture Block Diagram Table 18-2. Free Running Timer High Order Byte FRTMRH 0x21 R/WTable 18-3. Timer Configuration TMRCR 0x2A R/W 18.1.2 Time Capture Table 18-5. Timer Capture 0 Rising TCAP0R 0x22 R/W Table 18-4. Capture Interrupt Enable TCAPINTE 0x2B R/WTable 18-6. Timer Capture 1 Rising TCAP1R 0x23 R/W Table 18-7. Timer Capture 0 Falling TCAP0F 0x24 R/W 18.1.3 Programmable Interval Timer Table 18-8. Timer Capture 1 Falling TCAP1F 0x25 R/WTable 18-10. Programmable Interval Timer Low PITMRL 0x26 R Table 18-9. Capture Interrupt Status TCAPINTS 0x2C R/W Table 18-11. Programmable Interval Timer High PITMRH 0x27 R Table 18-12. Programmable Interval Reload Low PIRL 0x28 R/WTable 18-13. Programmable Interval Reload High PIRH 0x29 R/W Page 52 of Figure 18-3. Timer Functional Sequence Diagram Figure 18-5. Memory Mapped Registers Read and Write Timing Diagram Figure 18-4. 16-Bit Free Running Counter Loading Timing Diagram 19. Interrupt Controller Figure 19-1. Interrupt Controller Block Diagram19.1 Architectural Description Table 19-1. Interrupt Priorities, Address, and Name 19.3 Interrupt Latency 19.2 Interrupt Processing19.4 Interrupt Registers Table 19-2. Interrupt Clear 0 INTCLR0 0xDA R/W Interrupt Clear 2 INTCLR2 0xDC R/W Table 19-3. Interrupt Clear 1 INTCLR1 0xDB R/W19.4.2 Interrupt Mask Registers Table 19-5. Interrupt Mask 3 INTMSK3 0xDE R/W Table 19-6. Interrupt Mask 2 INTMSK2 0xDF R/W Table 19-7. Interrupt Mask 1 INTMSK1 0xE1 R/WPage 57 of Table 19-8. Interrupt Mask 0 INTMSK0 0xE0 R/W 19.4.3 Interrupt Vector Clear RegisterTable 19-9. Interrupt Vector Clear Register INTVC 0xE2 R/W 20. Absolute Maximum Ratings 20.1 DC CharacteristicsParameter Conditions Clock 20.2 AC CharacteristicsSPI Timing Figure 20-1. Clock Timing SCK CPOL=0 Figure 20-2. GPIO Timing DiagramSCK CPOL=1 MOSI MISO MISO MOSISS SCK CPOL=0 SCK CPOL=1 MOSI MISO MSB 22. Package Handling 21. Ordering InformationSCK CPOL=0 SCK CPOL=1 MOSI MSB Figure 23-1. 24-Pin 300-Mil SOIC S13 23. Package DiagramsFigure 23-2. 24-Pin 300-Mil PDIP P13 3. DIMENSIONS IN INCHES Figure 23-3. 24-Pin QSOP O241 Figure 23-4. 28-Pin 5.3 mm Shrunk Small Outline Package O28Page 65 of Figure 23-5. 40-Pin 600-Mil Molded DIP P17 Figure 23-6. 48-Pin Shrunk Small Outline Package O48Page 66 of Document Number 24. Document History PageOrig. of Submission PSoC Solutions Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products