Cypress manual Applications, Introduction, Conventions, CY7C601xx, CY7C602xx

CY7C601xx, CY7C602xx

3. Applications

The CY7C601xx and CY7C602xx are targeted for the following applications:

■PC wireless HID devices

❐Mice (optomechanical, optical, trackball)

❐Keyboards

❐Presenter tools

■Gaming

❐Joysticks

❐Gamepad

■General purpose wireless applications

❐Remote controls

❐Barcode scanners

❐POS terminal

❐Consumer electronics

❐Toys

4. Introduction

The enCoRe II LV family brings the features and benefits of the enCoRe II to non USB applications. The enCoRe II family has an integrated oscillator that eliminates the external crystal or resonator, reducing overall cost. Other external components, such as wakeup circuitry, are also integrated into this chip.

The enCoRe II LV is a low voltage, low cost 8-bit Flash program- mable microcontroller.

The enCoRe II LV features up to 36 GPIO pins. The IO pins are grouped into five ports (Port 0 to 4). The pins on Ports 0 and 1 are configured individually, when the pins on Ports 2, 3, and 4 are only configured as a group. Each GPIO port supports high impedance inputs, configurable pull up, open drain output, CMOS and TTL inputs, and CMOS output with up to five pins that support programmable drive strength of up to 50 mA sink current. Additionally, each IO pin is used to generate a GPIO interrupt to the microcontroller. Each GPIO port has its own GPIO interrupt vector with the exception of GPIO Port 0. GPIO Port 0 has, in addition to the port interrupt vector, three dedicated pins that have independent interrupt vectors (P0.2–P0.4).

The enCoRe II LV features an internal oscillator. Optionally, an external 1 MHz to 24 MHz crystal is used to provide a higher precision reference. The enCoRe II LV also supports external clock.

The enCoRe II LV has 8 Kbytes of Flash for user code and 256 bytes of RAM for stack space and user variables.

In addition, enCoRe II LV includes a watchdog timer, a vectored interrupt controller, a 16-bit free running timer with capture registers, and a 12-bit programmable interval timer. The power on reset circuit detects when power is applied to the device, resets the logic to a known state, and executes instructions at Flash address 0x0000. When power falls below a programmable trip voltage, it generates a reset or is configured to generate an interrupt. There is a low voltage detect circuit that detects when VCC drops below a programmable trip voltage. This is config- urable to generate a LVD interrupt to inform the processor about the low voltage event. POR and LVD share the same interrupt; there is no separate interrupt for each. The watchdog timer ensures the firmware never gets stalled in an infinite loop.

The microcontroller supports 17 maskable interrupts in the vectored interrupt controller. All interrupts can be masked. Interrupt sources include LVR or POR, a programmable interval timer, a nominal 1.024 ms programmable output from the free running timer, two capture timers, five GPIO ports, three GPIO pins, two SPI, a 16-bit free running timer wrap, and an internal wakeup timer interrupt. The wakeup timer causes periodic inter- rupts when enabled. The capture timers interrupt whenever a new timer value is saved due to a selected GPIO edge event. A total of eight GPIO interrupts support both TTL or CMOS thresholds. For additional flexibility, on the edge-sensitive GPIO pins, the interrupt polarity is programmable to be either rising or falling.

The free running timer generates an interrupt at 1024 μs rate. It also generates an interrupt when the free running counter overflow occurs—every 16.384 ms. The duration of an event under firmware control is measured by reading the timer at the start and end of an event, then calculating the difference between the two values. The two 8-bit capture timer registers save a programmable 8-bit range of the free running timer when a GPIO edge occurs on the two capture pins (P0.5 and P0.6). The two 8-bit capture registers are ganged into a single 16-bit capture register.

The enCoRe II LV supports in-system programming by using the P1.0 and P1.1 pins as the serial programming mode interface.

5. Conventions

In this document, bit positions in the registers are shaded to indicate which members of the enCoRe II LV family implement the bits.

Available in all enCoRe II LV family members

CY7C601xx only

Document 38-16016 Rev. *E Page 2 of 68

[+] Feedback