8. Timer Capture 1 Falling TCAP1F 0x25 R/W | Cypress CY7C601xx

Table 18-8. Timer Capture 1 Falling (TCAP1F) [0x25] [R/W]

CY7C601xx, CY7C602xx

Table 18-8. Timer Capture 1 Falling (TCAP1F) [0x25] [R/W]

Bit #	7	6	5	4	3	2	1	0
Field				Capture 1 Falling [7:0]
Read/Write	R	R	R	R	R	R	R	R
Default	0	0	0	0	0	0	0	0

Bit [7:0]: Capture 1 Falling [7:0]

This register holds the value of the free running timer when the last falling edge occurred on the TIO1 input. The bits stored here are selected by the Prescale [2:0] bits in the Timer Configuration register. When capture 0 is in 16-bit mode this register holds the high order eight bits of the 16-bit timer from the last TIO0 falling edge.

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Table 18-9. Capture Interrupt Status (TCAPINTS) [0x2C] [R/W]

Bit #	7	6		5	4	3	2	1	0
Field			Reserved			Cap1 Fall	Cap1 Rise	Cap0 Fall	Cap0 Rise
						Active	Active	Active	Active
Read/Write	–	–		–	–	R/W	R/W	R/W	R/W
Default	0	0		0	0	0	0	0	0

These four bits contains the status bits for the four timer captures for the four timer block capture interrupt sources. Writing any of these bits with 1 clears that interrupt.

Bit [7:4]: Reserved

Bit 3: Cap1 Fall Active 0 = No event

1 = A falling edge has occurred on TIO1 Bit 2: Cap1 Rise Active

0 = No event

1 = A rising edge has occurred on TIO1 Bit 1: Cap0 Fall Active

0 = No event

1 = A falling edge has occurred on TIO0 Bit 0: Cap0 Rise Active

0 = No event

1 = A rising edge has occurred on TIO0

Note The interrupt status bits are cleared by firmware to enable subsequent interrupts. This is achieved by writing a ‘1’ to the corresponding Interrupt status bit.

18.1.3 Programmable Interval Timer

Table 18-10. Programmable Interval Timer Low (PITMRL) [0x26] [R]

Bit #	7	6	5	4	3	2	1	0
Field				Prog Interval Timer [7:0]
Read/Write	R	R	R	R	R	R	R	R
Default	0	0	0	0	0	0	0	0

Bit [7:0]: Prog Interval Timer [7:0]

This register holds the low order byte of the 12-bit programmable interval timer. Reading this register moves the high order byte into a holding register allowing an automatic read of all 12 bits simultaneously.

Document 38-16016 Rev. *E

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Cypress CY7C601xx, CY7C602xx 8. Timer Capture 1 Falling TCAP1F 0x25 R/W, 9. Capture Interrupt Status TCAPINTS 0x2C R/W

Contents

CY7C601xx, CY7C602xx 1. Features2. Logic Block Diagram Cypress Semiconductor Corporation 5. Conventions 3. Applications4. Introduction CY7C60223 Figure 6-1. Package Configurations Top View6. Pinouts 24-Pin PDIP Table 6-1. Pin Assignments CY7C601xx, CY7C602xx6.1 Pin Assignments Name Table 6-1. Pin Assignments continued Table 7-1. enCoRe II LV Register Summary Default7. Register Summary Addr Table 7-1. enCoRe II LV Register Summary continued 9.1 Flags Register 8. CPU Architecture9. CPU Registers Table 8-1. CPU Registers and Register Name 9.1.2 Index Register 9.1.1 Accumulator RegisterTable 9-2. CPU Accumulator Register CPUA Table 9-3. CPU X Register CPUX Table 9-7. Source Immediate 9.2 Addressing Modes9.2.1 Source Immediate Opcode Example 9.2.5 Destination IndexedTable 9-11. Destination Indexed 9.2.6 Destination Direct Source Immediate Table 9-15. Source Indirect Post Increment 10. Instruction Set Summary9.2.9 Source Indirect Post Increment 9.2.10 Destination Indirect Post Increment Bytes Figure 11-1. Program Memory Space with Interrupt Vector Table 11. Memory Organization11.1 Flash Program Memory Organization 0x1FFF 11.4 SROM 11.2 Data Memory Organization11.3 Flash Figure 11-2. Data Memory Organization Table 11-2. SROM Function Parameters 11.5.1 SWBootReset Function11.5 SROM Function Descriptions Variable Name Table 11-5. WriteBlock Parameters Settings11.5.3 WriteBlock Function 11.5.4 EraseBlock Function 11.5.7 TableRead Function Table 11-8. ProtectBlock Parameters11.5.6 EraseAll Function Table 11-10. Table Read Parameters 11.6 SROM Table Read Description Page 19 of eg ti 12.1 Trim Values for the IOSCTR Register Table 12-1. Oscillator Trim Values vs. Voltage Settings12. Clocking Gain value for the register at location 0x38 3.3V = 12.2 Clock Architecture Description 12.2.1 CPU Clock Bit 71 Reserved Figure 12-1. CPU Clock Block DiagramTable 12-2. CPU Clock Configuration CPUCLKCR 0x30 R/W Table 12-3. OSC Control 0 OSCCR0 0x1E0 R/W CPU when Internal Sleep TimerSleep Timer Clock Table 12-3. OSC Control 0 OSCCR0 0x1E0 R/W continued Bit 75 Reserved Table 12-4. Clock IO Configuration CLKIOCR 0x32 R/W12.2.2 Interval Timer Clock ITMRCLK Figure 12-3. Timer Capture Block Diagram Figure 12-2. Programmable Interval Timer Block Diagram12.2.3 Timer Capture Clock TCAPCLK Table 12-5. Timer Clock Configuration TMRCLKCR 0x31 R/W Page 27 of Table 12-6. IOSC Trim IOSCTR 0x34 R/W XGM Setting12.2.4 Internal Clock Trim Bit 40 Gain Table 12-8. LPOSC Trim LPOSCTR 0x36 R/W 12.3 CPU Clock During Sleep Mode12.2.6 LPOSC Trim Bit 7 GIES 13. ResetTable 13-1. System Status and Control Register CPUSCR 0xFF R/W Bit 5 WDRS Table 13-2. Reset Watchdog Timer RESWDT 0xE3 W 13.1 Power On Reset13.2 Watchdog Timer Reset 14. Sleep Mode CPUCLK IOW SLEEP BRQ BRA PD 14.1.1 Low Power in Sleep Mode14.1 Sleep Sequence Figure 14-1. Sleep Timing 14.2 Wakeup Sequence Figure 14-2. Wakeup Timing Bit 76 Reserved Bit 54 PORLEV10 15. Low Voltage Detect ControlTable 15-1. Low Voltage Control Register LVDCR 0x1E3 R/W Bit 20 VM20 Table 15-2. Voltage Monitor Comparators Register VLTCMP 0x1E4 R 15.1 POR Compare State15.2 ECO Trim Register Bit 72 Reserved Bit 1 LVD 16.1.1 P0 Data 16. General Purpose IO Ports16.1 Port Data Registers Table 16-1. P0 Data Register P0DATA0x00 R/W 16.1.3 P2 Data 16.2 GPIO Port Configuration16.2.1 Int Enable Table 16-3. P2 Data Register P2DATA 0x02 R/W Figure 16-1. GPIO Block Diagram 16.2.7 Output Enable16.2.6 Pull Up Enable 16.2.9 P0.0/CLKIN Configuration 16.2.11 P0.2/INT0-P0.4/INT2 Configuration 16.2.10 P0.1/CLKOUT ConfigurationTable 16-7. P0.1/CLKOUT Configuration P01CR 0x06 R/W Table 16-10. P0.7 Configuration P07CR 0x0C R/W 16.2.12 P0.5/TIO0-P0.6/TIO1 Configuration16.2.13 P0.7 Configuration 16.2.14 P1.0 Configuration 16.2.16 P1.2 Configuration 16.2.15 P1.1 ConfigurationTable 16-12. P1.1 Configuration P11CR 0x0E R/W Table 16-13. P1.2 Configuration P12CR 0x0F R/W 16.2.19 P1.7 Configuration 16.2.18 P1.4-P1.6 Configuration SCLK, SMOSI, SMISOTable 16-15. P1.4-P1.6 Configuration P14CR-P16CR 0x11-0x13 R/W Table 16-16. P1.7 Configuration P17CR 0x14 R/W 16.2.22 P4 Configuration 16.2.21 P3 ConfigurationTable 16-18. P3 Configuration P3CR 0x16 R/W Table 16-19. P4 Configuration P4CR 0x17 R/W Figure 17-1. SPI Block Diagram 17. Serial Peripheral Interface SPI 17.1 SPI Data Register 17.2 SPI Configure RegisterTable 17-2. SPI Configure Register SPICR 0x3D R/W Table 17-1. SPI Data Register SPIDATA 0x3C R/W CPHA Table 17-3. SPI Mode Timing vs. LSB First, CPOL, and CPHADiagram CPOL Figure 18-1. 16-Bit Free Running Counter Block Diagram 18. Timer Registers17.3 SPI Interface Pins Table 18-1. Free Running Timer Low Order Byte FRTMRL 0x20 R/W Table 18-3. Timer Configuration TMRCR 0x2A R/W Table 18-2. Free Running Timer High Order Byte FRTMRH 0x21 R/WFigure 18-2. Time Capture Block Diagram 18.1.2 Time Capture Table 18-6. Timer Capture 1 Rising TCAP1R 0x23 R/W Table 18-4. Capture Interrupt Enable TCAPINTE 0x2B R/WTable 18-5. Timer Capture 0 Rising TCAP0R 0x22 R/W Table 18-7. Timer Capture 0 Falling TCAP0F 0x24 R/W Table 18-10. Programmable Interval Timer Low PITMRL 0x26 R Table 18-8. Timer Capture 1 Falling TCAP1F 0x25 R/W18.1.3 Programmable Interval Timer Table 18-9. Capture Interrupt Status TCAPINTS 0x2C R/W Table 18-13. Programmable Interval Reload High PIRH 0x29 R/W Table 18-11. Programmable Interval Timer High PITMRH 0x27 RTable 18-12. Programmable Interval Reload Low PIRL 0x28 R/W Figure 18-3. Timer Functional Sequence Diagram Page 52 of Figure 18-4. 16-Bit Free Running Counter Loading Timing Diagram Figure 18-5. Memory Mapped Registers Read and Write Timing Diagram 19.1 Architectural Description Figure 19-1. Interrupt Controller Block Diagram19. Interrupt Controller Table 19-1. Interrupt Priorities, Address, and Name 19.4 Interrupt Registers 19.2 Interrupt Processing19.3 Interrupt Latency Table 19-2. Interrupt Clear 0 INTCLR0 0xDA R/W 19.4.2 Interrupt Mask Registers Table 19-3. Interrupt Clear 1 INTCLR1 0xDB R/WInterrupt Clear 2 INTCLR2 0xDC R/W Table 19-5. Interrupt Mask 3 INTMSK3 0xDE R/W Page 57 of Table 19-6. Interrupt Mask 2 INTMSK2 0xDF R/WTable 19-7. Interrupt Mask 1 INTMSK1 0xE1 R/W Table 19-9. Interrupt Vector Clear Register INTVC 0xE2 R/W Table 19-8. Interrupt Mask 0 INTMSK0 0xE0 R/W19.4.3 Interrupt Vector Clear Register Parameter 20.1 DC Characteristics20. Absolute Maximum Ratings Conditions SPI Timing 20.2 AC CharacteristicsClock Figure 20-1. Clock Timing SCK CPOL=1 Figure 20-2. GPIO Timing DiagramSCK CPOL=0 MOSI MISO SS SCK CPOL=0 SCK CPOL=1 MOSIMISO MOSI MISO MSB SCK CPOL=0 SCK CPOL=1 21. Ordering Information22. Package Handling MOSI MSB Figure 23-2. 24-Pin 300-Mil PDIP P13 23. Package DiagramsFigure 23-1. 24-Pin 300-Mil SOIC S13 3. DIMENSIONS IN INCHES Page 65 of Figure 23-3. 24-Pin QSOP O241Figure 23-4. 28-Pin 5.3 mm Shrunk Small Outline Package O28 Page 66 of Figure 23-5. 40-Pin 600-Mil Molded DIP P17Figure 23-6. 48-Pin Shrunk Small Outline Package O48 Orig. of 24. Document History PageDocument Number Submission Worldwide Sales and Design Support Sales, Solutions, and Legal InformationPSoC Solutions Products