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Cypress CY7C601xx 3. OSC Control 0 OSCCR0 0x1E0 R/W continued, Bit 76 Reserved Bit 5 No Buzz

Models: CY7C601xx CY7C602xx

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Table 12-3. OSC Control 0 (OSC_CR0) [0x1E0] [R/W] (continued)

CY7C601xx, CY7C602xx

Table 12-3. OSC Control 0 (OSC_CR0) [0x1E0] [R/W] (continued)

Read/Write	–	–	R/W	R/W	R/W	R/W	R/W	R/W
Default	0	0	0	0	0	0	0	0

Bit [7:6]: Reserved

Bit 5: No Buzz

During sleep (the Sleep bit is set in the CPU_SCR Register—Table13-1), the LVD and POR detection circuit is turned on periodically to detect any POR and LVD events on the VCC pin (the Sleep Duty Cycle bits in the ECO_TR are used to control the duty cycle—Table15-3). To facilitate the detection of POR and LVD events, the No Buzz bit is used to continuously enable the LVD and POR detection circuit during sleep. This results in a faster response to an LVD or POR event during sleep at the expense of a slightly higher than average sleep current. Obtaining the absolute lowest power usage in sleep mode requires the No Buzz bit be clear.

0 = The LVD and POR detection circuit is turned on periodically as configured in the Sleep Duty Cycle.

1 = The Sleep Duty Cycle value is overridden. The LVD and POR detection circuit is always enabled.

Note The periodic Sleep Duty Cycle enabling is independent with the sleep interval shown in the Sleep [1:0] bits below. Bit [4:3]: Sleep Timer [1:0]

Sleep Timer	Sleep Timer Clock	Sleep Period	Watchdog Period
[1:0]	Frequency (Nominal)	(Nominal)	(Nominal)
00	512 Hz	1.95 ms	6 ms

01	64 Hz	15.6 ms	47 ms

10	8 Hz	125 ms	375 ms

11	1 Hz	1 sec	3 sec

Note Sleep intervals are approximate. Bit [2:0]: CPU Speed [2:0]

The enCoRe II LV operates over a range of CPU clock speeds. The reset value for the CPU Speed bits is zero; therefore, the default CPU speed is 3 MHz.

CPU Speed	CPU when Internal	External Clock
[2:0]	Oscillator is selected	External Clock
000	3 MHz (Default)	Clock In/8
001	6 MHz	Clock In/4
010	12 MHz	Clock In/2
011	Reserved	Reserved
100	1.5 MHz	Clock In/16
101	750 KHz	Clock In/32
110	187 KHz	Clock In/128
111	Reserved	Reserved

Note This register exists in the second bank of IO space. This requires setting the XIO bit in the CPU flags register.

Document 38-16016 Rev. *E

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Cypress CY7C601xx 3. OSC Control 0 OSCCR0 0x1E0 R/W continued, Bit 76 Reserved Bit 5 No Buzz, Sleep Timer, Sleep Period

Contents

1. Features 2. Logic Block DiagramCY7C601xx, CY7C602xx Cypress Semiconductor Corporation3. Applications 4. Introduction5. Conventions CY7C601xx, CY7C602xxFigure 6-1. Package Configurations Top View 6. PinoutsCY7C60223 24-Pin PDIPCY7C601xx, CY7C602xx 6.1 Pin AssignmentsTable 6-1. Pin Assignments NameTable 6-1. Pin Assignments continued CY7C601xx, CY7C602xxName DescriptionDefault 7. Register SummaryTable 7-1. enCoRe II LV Register Summary AddrTable 7-1. enCoRe II LV Register Summary continued DefaultCY7C601xx, CY7C602xx Addr8. CPU Architecture 9. CPU Registers9.1 Flags Register Table 8-1. CPU Registers and Register Name9.1.1 Accumulator Register Table 9-2. CPU Accumulator Register CPUA9.1.2 Index Register Table 9-3. CPU X Register CPUX9.2 Addressing Modes 9.2.1 Source ImmediateTable 9-7. Source Immediate Opcode9.2.5 Destination Indexed Table 9-11. Destination IndexedExample 9.2.6 Destination Direct Source Immediate10. Instruction Set Summary 9.2.9 Source Indirect Post IncrementTable 9-15. Source Indirect Post Increment 9.2.10 Destination Indirect Post IncrementCY7C601xx, CY7C602xx CyclesBytes Flags11. Memory Organization 11.1 Flash Program Memory OrganizationFigure 11-1. Program Memory Space with Interrupt Vector Table 0x1FFF11.2 Data Memory Organization 11.3 Flash11.4 SROM Figure 11-2. Data Memory Organization11.5.1 SWBootReset Function 11.5 SROM Function DescriptionsTable 11-2. SROM Function Parameters Variable NameSettings 11.5.3 WriteBlock FunctionTable 11-5. WriteBlock Parameters 11.5.4 EraseBlock FunctionTable 11-8. ProtectBlock Parameters 11.5.6 EraseAll Function11.5.7 TableRead Function Table 11-10. Table Read Parameters11.6 SROM Table Read Description CY7C601xx, CY7C602xxPage 19 of CY7C601xx, CY7C602xx eg tiTable 12-1. Oscillator Trim Values vs. Voltage Settings 12. Clocking12.1 Trim Values for the IOSCTR Register Gain value for the register at location 0x38 3.3V =12.2 Clock Architecture Description 12.2.1 CPU ClockCY7C601xx, CY7C602xx Figure 12-1. CPU Clock Block Diagram Table 12-2. CPU Clock Configuration CPUCLKCR 0x30 R/WBit 71 Reserved Table 12-3. OSC Control 0 OSCCR0 0x1E0 R/WSleep Timer Sleep Timer ClockCPU when Internal Table 12-3. OSC Control 0 OSCCR0 0x1E0 R/W continuedTable 12-4. Clock IO Configuration CLKIOCR 0x32 R/W 12.2.2 Interval Timer Clock ITMRCLKBit 75 Reserved CY7C601xx, CY7C602xxFigure 12-2. Programmable Interval Timer Block Diagram 12.2.3 Timer Capture Clock TCAPCLKFigure 12-3. Timer Capture Block Diagram CY7C601xx, CY7C602xxTable 12-5. Timer Clock Configuration TMRCLKCR 0x31 R/W CY7C601xx, CY7C602xxPage 27 of XGM Setting Bit 0 Mode12.2.4 Internal Clock Trim Table 12-6. IOSC Trim IOSCTR 0x34 R/W12.3 CPU Clock During Sleep Mode 12.2.6 LPOSC TrimTable 12-8. LPOSC Trim LPOSCTR 0x36 R/W CY7C601xx, CY7C602xx13. Reset Table 13-1. System Status and Control Register CPUSCR 0xFF R/WBit 7 GIES Bit 5 WDRS14. Sleep Mode 13.1 Power On Reset13.2 Watchdog Timer Reset Table 13-2. Reset Watchdog Timer RESWDT 0xE3 W14.1.1 Low Power in Sleep Mode 14.1 Sleep SequenceCPUCLK IOW SLEEP BRQ BRA PD Figure 14-1. Sleep Timing14.2 Wakeup Sequence Figure 14-2. Wakeup TimingCY7C601xx, CY7C602xx 15. Low Voltage Detect Control Table 15-1. Low Voltage Control Register LVDCR 0x1E3 R/WBit 76 Reserved Bit 54 PORLEV10 Bit 20 VM2015.1 POR Compare State 15.2 ECO Trim RegisterTable 15-2. Voltage Monitor Comparators Register VLTCMP 0x1E4 R Bit 72 Reserved Bit 1 LVD16. General Purpose IO Ports 16.1 Port Data Registers16.1.1 P0 Data Table 16-1. P0 Data Register P0DATA0x00 R/W16.2 GPIO Port Configuration 16.2.1 Int Enable16.1.3 P2 Data Table 16-3. P2 Data Register P2DATA 0x02 R/W16.2.7 Output Enable 16.2.6 Pull Up EnableFigure 16-1. GPIO Block Diagram 16.2.9 P0.0/CLKIN Configuration16.2.10 P0.1/CLKOUT Configuration Table 16-7. P0.1/CLKOUT Configuration P01CR 0x06 R/W16.2.11 P0.2/INT0-P0.4/INT2 Configuration CY7C601xx, CY7C602xx16.2.12 P0.5/TIO0-P0.6/TIO1 Configuration 16.2.13 P0.7 ConfigurationTable 16-10. P0.7 Configuration P07CR 0x0C R/W 16.2.14 P1.0 Configuration16.2.15 P1.1 Configuration Table 16-12. P1.1 Configuration P11CR 0x0E R/W16.2.16 P1.2 Configuration Table 16-13. P1.2 Configuration P12CR 0x0F R/W16.2.18 P1.4-P1.6 Configuration SCLK, SMOSI, SMISO Table 16-15. P1.4-P1.6 Configuration P14CR-P16CR 0x11-0x13 R/W16.2.19 P1.7 Configuration Table 16-16. P1.7 Configuration P17CR 0x14 R/W16.2.21 P3 Configuration Table 16-18. P3 Configuration P3CR 0x16 R/W16.2.22 P4 Configuration Table 16-19. P4 Configuration P4CR 0x17 R/WFigure 17-1. SPI Block Diagram 17. Serial Peripheral Interface SPICY7C601xx, CY7C602xx 17.2 SPI Configure Register Table 17-2. SPI Configure Register SPICR 0x3D R/W17.1 SPI Data Register Table 17-1. SPI Data Register SPIDATA 0x3C R/WTable 17-3. SPI Mode Timing vs. LSB First, CPOL, and CPHA DiagramCY7C601xx, CY7C602xx CPHA18. Timer Registers 17.3 SPI Interface PinsFigure 18-1. 16-Bit Free Running Counter Block Diagram Table 18-1. Free Running Timer Low Order Byte FRTMRL 0x20 R/WTable 18-2. Free Running Timer High Order Byte FRTMRH 0x21 R/W Figure 18-2. Time Capture Block DiagramTable 18-3. Timer Configuration TMRCR 0x2A R/W 18.1.2 Time CaptureTable 18-4. Capture Interrupt Enable TCAPINTE 0x2B R/W Table 18-5. Timer Capture 0 Rising TCAP0R 0x22 R/WTable 18-6. Timer Capture 1 Rising TCAP1R 0x23 R/W Table 18-7. Timer Capture 0 Falling TCAP0F 0x24 R/WTable 18-8. Timer Capture 1 Falling TCAP1F 0x25 R/W 18.1.3 Programmable Interval TimerTable 18-10. Programmable Interval Timer Low PITMRL 0x26 R Table 18-9. Capture Interrupt Status TCAPINTS 0x2C R/WTable 18-11. Programmable Interval Timer High PITMRH 0x27 R Table 18-12. Programmable Interval Reload Low PIRL 0x28 R/WTable 18-13. Programmable Interval Reload High PIRH 0x29 R/W CY7C601xx, CY7C602xxFigure 18-3. Timer Functional Sequence Diagram CY7C601xx, CY7C602xxPage 52 of + FeedbackFigure 18-4. 16-Bit Free Running Counter Loading Timing Diagram Figure 18-5. Memory Mapped Registers Read and Write Timing DiagramCY7C601xx, CY7C602xx + FeedbackFigure 19-1. Interrupt Controller Block Diagram 19. Interrupt Controller19.1 Architectural Description Table 19-1. Interrupt Priorities, Address, and Name19.2 Interrupt Processing 19.3 Interrupt Latency19.4 Interrupt Registers Table 19-2. Interrupt Clear 0 INTCLR0 0xDA R/WTable 19-3. Interrupt Clear 1 INTCLR1 0xDB R/W Interrupt Clear 2 INTCLR2 0xDC R/W19.4.2 Interrupt Mask Registers Table 19-5. Interrupt Mask 3 INTMSK3 0xDE R/WTable 19-6. Interrupt Mask 2 INTMSK2 0xDF R/W Table 19-7. Interrupt Mask 1 INTMSK1 0xE1 R/WCY7C601xx, CY7C602xx Page 57 ofTable 19-8. Interrupt Mask 0 INTMSK0 0xE0 R/W 19.4.3 Interrupt Vector Clear RegisterTable 19-9. Interrupt Vector Clear Register INTVC 0xE2 R/W CY7C601xx, CY7C602xx20.1 DC Characteristics 20. Absolute Maximum RatingsParameter Conditions20.2 AC Characteristics ClockSPI Timing Figure 20-1. Clock TimingFigure 20-2. GPIO Timing Diagram SCK CPOL=0SCK CPOL=1 MOSI MISOMOSI MISOSS SCK CPOL=0 SCK CPOL=1 MOSI MISO MSBBake Temperature 21. Ordering Information22. Package Handling SCK CPOL=0 SCK CPOL=123. Package Diagrams Figure 23-1. 24-Pin 300-Mil SOIC S13Figure 23-2. 24-Pin 300-Mil PDIP P13 3. DIMENSIONS IN INCHESFigure 23-3. 24-Pin QSOP O241 Figure 23-4. 28-Pin 5.3 mm Shrunk Small Outline Package O28CY7C601xx, CY7C602xx Page 65 ofFigure 23-5. 40-Pin 600-Mil Molded DIP P17 Figure 23-6. 48-Pin Shrunk Small Outline Package O48CY7C601xx, CY7C602xx Page 66 of24. Document History Page Document NumberOrig. of SubmissionSales, Solutions, and Legal Information PSoC SolutionsWorldwide Sales and Design Support Products