Cypress AC Characteristics, SPI Timing, 1. Clock Timing, CY7C601xx, CY7C602xx, Parameter

CY7C601xx, CY7C602xx

20.2 AC Characteristics

Parameter	Description		Conditions		Min	Typical	Max	Unit
Clock
TECLKDC	External Clock Duty Cycle				45		55	%
TECLK2	External Clock Frequency				1		24	MHz
FIMO	Internal Main Oscillator Frequency	With proper trim values loaded[5]			18.72		26.4	MHz
FILO	Internal Low Power Oscillator	With proper trim values loaded[5]			15.0001		50.0	KHz
GPIO Timing
TR_GPIO	Output Rise Time	Measured between 10 and 90% Vdd					50	ns
		and Vreg with 50 pF load
TF_GPIO	Output Fall Time	Measured between 10 and 90% Vdd					15	ns
		and Vreg with 50 pF load
SPI Timing
TSMCK	SPI Master Clock Rate	FCPUCLK/6					2	MHz
TSSCK	SPI Slave Clock Rate						2.2	MHz
TSCKH	SPI Clock High Time	High for CPOL = 0, Low for CPOL = 1			125			ns
TSCKL	SPI Clock Low Time	Low for CPOL = 0, High for CPOL = 1			125			ns
T	Master Data Output Time[6]	SCK to data valid			–25		50	ns
MDO
TMDO1	Master Data Output Time,	Time before leading SCK edge			100			ns
	First bit with CPHA = 0
TMSU	Master Input Data Setup time				50			ns
TMHD	Master Input Data Hold time				50			ns
TSSU	Slave Input Data Setup Time				50			ns
TSHD	Slave Input Data Hold Time				50			ns
TSDO	Slave Data Output Time	SCK to data valid					100	ns
TSDO1	Slave Data Output Time,	Time after	SS	LOW to data valid			100	ns
	First bit with CPHA = 0
TSSS	Slave Select Setup Time	Before first SCK edge			150			ns
TSSH	Slave Select Hold Time	After last SCK edge			150			ns

Figure 20-1. Clock Timing

CLOCK

TCYC TCH

TCL

Document 38-16016 Rev. *E Page 60 of 68

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