CY7C6431x CY7C64345, CY7C6435x
Functional Overview
The enCoRe V family of devices are designed to replace multiple traditional full speed USB microcontroller system components with one, low cost
The architecture for this device family, as illustrated in the “enCoRe V Block Diagram” on page 1, consists of two main areas: the CPU core and the system resources. Depending on the enCoRe V package, up to 36 general purpose I/O (GPIO) are also included.
This product is an enhanced version of Cypress’s successful full speed USB peripheral controllers. Enhancements include faster CPU at lower voltage operation, lower current consumption, twice the RAM and Flash,
The enCoRe V Core
The enCoRe V Core is a powerful engine that supports a rich instruction set. It encompasses SRAM for data storage, an interrupt controller, sleep and watchdog timers, and IMO (internal main oscillator) and ILO (internal low speed oscillator). The CPU core, called the M8C, is a powerful processor with speeds up to 24 MHz. The M8C is a
System resources provide additional capability, such as a config- urable I2C slave and SPI
Additional System Resources
System resources, some of which have been previously listed, provide additional capability useful to complete systems. Additional resources include low voltage detection and power on reset. The following statements describe the merits of each system resource.
■Full speed USB (12 Mbps) with nine configurable endpoints and 512 bytes of dedicated USB RAM. No external components are required except two series resistors. It is specified for commercial temperature USB operation. For reliable USB operation, ensure the supply voltage is between 4.35V and 5.25V, or around 3.3V.
■8 bit
■The I2C slave and SPI
■In I2C slave mode, the hardware address recognition feature reduces the already low power consumption by eliminating the
need for CPU intervention until a packet addressed to the target device is received.
■Low Voltage Detection (LVD) interrupts can signal the appli- cation of falling voltage levels, while the advanced POR (power on reset) circuit eliminates the need for a system supervisor.
■The 5V maximum input, 1.8, 2.5, or 3V selectable output, low dropout regulator (LDO) provides regulation for I/Os. A register controlled bypass mode enables the user to disable the LDO.
■Standard Cypress PSoC IDE tools are available for debugging the enCoRe V family of parts.
Getting Started
The quickest path to understanding the enCoRe V silicon is by reading this data sheet and using the PSoC Designer Integrated Development Environment (IDE). This data sheet is an overview of the enCoRe V integrated circuit and presents specific pin, register, and electrical specifications. For
For
Development Kits
Development Kits are available online from Cypress at www.cypress.com/shop and through a growing number of regional and global distributors, which include Arrow, Avnet,
Technical Training Modules
Free technical training (on demand, webinars, and workshops) is available online at www.cypress.com/training. The training covers a wide variety of topics and skill levels to assist you in your designs.
Consultants
Certified USB consultants offer everything from technical assis- tance to completed PSoC designs. To contact or become a PSoC Consultant go to www.cypress.com/cypros.
Technical Support
For assistance with technical issues, search KnowledgeBase articles and forums at www.cypress.com/support. If you cannot find an answer to your question, call technical support at
Application Notes
Application notes are an excellent introduction to the wide variety of possible PSoC designs. They are located here: www.cypress.com/psoc. Select Application Notes under the Documentation tab.
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