CY7C6431x
CY7C64345, CY7C6435x
Document Number: 001-12394 Rev *G Page 22 of 28
AC I2C Specifications
Tabl e 21 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Figure 8. Definition of Timing for Fast/Standard Mode on the I2C Bus
Table 21. AC Characteristics of the I2C SDA and SCL Pins
Symbol Description Standard Mode Fast Mode Units
Min Max Min Max
FSCLI2C SCL Clock Frequency 0 100 0 400 kHz
THDSTAI2C Hold Time (repeated) START Condition. After this period, the first
clock pulse is generated. 4.0 –0.6–μs
TLOWI2C LOW Period of the SCL Clock 4.7 –1.3–μs
THIGHI2C HIGH Period of the SCL Clock 4.0 –0.6–μs
TSUSTAI2C Setup Time for a Repeated START Condition 4.7 –0.6–μs
THDDATI2C Data Hold Time 0 –0–μs
TSUDATI2C Data Setup Time 250 –100
(15) –ns
TSUSTOI2C Setup Time for STOP Condition 4.0 –0.6–μs
TBUFI2C Bus Free Time Between a STOP and START Condition 4.7 –1.3–μs
TSPI2C Pulse Width of spikes are suppressed by the input filter. –– 0 50 ns
Notes
15.A Fast mode I2C bus device can be used in a standard mode I2C bus system, but the requirement tSU;DAT ≥ 250 ns must then be met. This is automatically the case if the device does not stretch the
LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the
standard mode I2C bus specification) before the SCL line is released.
SDA
SCL
SSr SP
TBUFI2C
TSPI2C
THDSTAI2C
TSUSTOI2C
TSUSTAI2C
TLOWI2C
THIGHI2C
THDDATI2C
THDSTAI2C
TSUDATI2C
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