Cypress CY8C21534, CY8C21334, CY8C21634 manual AC Analog Mux Bus Specifications, Switch Rate MHz

CY8C21634, CY8C21534

CY8C21434, CY8C21334, CY8C21234

AC Analog Mux Bus Specifications

Table 31 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C

≤TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only.

Table 31. AC Analog Mux Bus Specifications

Symbol	Description	Min	Typ	Max	Units	Notes
FSW	Switch Rate	–	–	3.17	MHz

AC Digital Block Specifications

The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only.

Table 32. 5V and 3.3V AC Digital Block Specifications

Function	Description	Min	Typ	Max	Units	Notes
All	Maximum Block Clocking Frequency (> 4.75V)			49.2	MHz	4.75V < Vdd < 5.25V.
Functions
	Maximum Block Clocking Frequency (< 4.75V)			24.6	MHz	3.0V < Vdd < 4.75V.
Timer	Capture Pulse Width	50[19]	–	–	ns
	Maximum Frequency, No Capture	–	–	49.2	MHz	4.75V < Vdd < 5.25V.
	Maximum Frequency, With or Without Capture	–	–	24.6	MHz
Counter	Enable Pulse Width	50	–	–	ns
	Maximum Frequency, No Enable Input	–	–	49.2	MHz	4.75V < Vdd < 5.25V.
	Maximum Frequency, Enable Input	–	–	24.6	MHz
Dead Band	Kill Pulse Width:
	Asynchronous Restart Mode	20	–	–	ns
	Synchronous Restart Mode	50	–	–	ns
	Disable Mode	50	–	–	ns
	Maximum Frequency	–	–	49.2	MHz	4.75V < Vdd < 5.25V.
CRCPRS	Maximum Input Clock Frequency	–	–	49.2	MHz	4.75V < Vdd < 5.25V.
(PRS
Mode)
CRCPRS	Maximum Input Clock Frequency	–	–	24.6	MHz
(CRC
Mode)
SPIM	Maximum Input Clock Frequency	–	–	8.2	MHz	Maximum data rate at 4.1 MHz
						due to 2 x over clocking.
SPIS	Maximum Input Clock Frequency	–	–	4.1	MHz
	Width of SS_ Negated Between Transmissions	50	–	–	ns
Transmitter	Maximum Input Clock Frequency	–	–	24.6	MHz	Maximum data rate at 3.08 MHz
						due to 8 x over clocking.
	Maximum Input Clock Frequency with Vdd ≥	–	–	49.2	MHz	Maximum data rate at 6.15 MHz
	4.75V, 2 Stop Bits					due to 8 x over clocking.
Receiver	Maximum Input Clock Frequency	–	–	24.6	MHz	Maximum data rate at 3.08 MHz
	Maximum Input Clock Frequency with Vdd ≥					due to 8 x over clocking.
		–	–	49.2	MHz	Maximum data rate at 6.15 MHz
	4.75V, 2 Stop Bits					due to 8 x over clocking.

Note

19. 50 ns minimum input pulse width is based on the input synchronizers running at 12 MHz (84 ns nominal period).

Document Number: 38-12025 Rev. *O Page 29 of 45

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