Cypress manual CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234

CY8C21634, CY8C21534

CY8C21434, CY8C21334, CY8C21234

Table 10. Register Map 1 Table: Configuration Space (continued)

Name	Addr (1,Hex)	Access	Name	Addr (1,Hex)	Access	Name	Addr (1,Hex)	Access	Name	Addr (1,Hex)	Access
	15			55			95			D5
	16			56			96			D6
	17			57			97			D7
	18			58			98		MUX_CR0	D8	RW
	19			59			99		MUX_CR1	D9	RW
	1A			5A			9A		MUX_CR2	DA	RW
	1B			5B			9B		MUX_CR3	DB	RW
	1C			5C			9C			DC
	1D			5D			9D		OSC_GO_EN	DD	RW
	1E			5E			9E		OSC_CR4	DE	RW
	1F			5F			9F		OSC_CR3	DF	RW
DBB00FN	20	RW	CLK_CR0	60	RW		A0		OSC_CR0	E0	RW
DBB00IN	21	RW	CLK_CR1	61	RW		A1		OSC_CR1	E1	RW
DBB00OU	22	RW	ABF_CR0	62	RW		A2		OSC_CR2	E2	RW
	23		AMD_CR0	63	RW		A3		VLT_CR	E3	RW
DBB01FN	24	RW	CMP_GO_EN	64	RW		A4		VLT_CMP	E4	R
DBB01IN	25	RW		65			A5		ADC0_TR	E5	RW
DBB01OU	26	RW	AMD_CR1	66	RW		A6		ADC1_TR	E6	RW
	27		ALT_CR0	67	RW		A7			E7
DCB02FN	28	RW		68			A8		IMO_TR	E8	W
DCB02IN	29	RW		69			A9		ILO_TR	E9	W
DCB02OU	2A	RW		6A			AA		BDG_TR	EA	RW
	2B		CLK_CR3	6B	RW		AB		ECO_TR	EB	W
DCB03FN	2C	RW	TMP_DR0	6C	RW		AC			EC
DCB03IN	2D	RW	TMP_DR1	6D	RW		AD			ED
DCB03OU	2E	RW	TMP_DR2	6E	RW		AE			EE
	2F		TMP_DR3	6F	RW		AF			EF
	30			70		RDI0RI	B0	RW		F0
	31			71		RDI0SYN	B1	RW		F1
	32		ACE00CR1	72	RW	RDI0IS	B2	RW		F2
	33		ACE00CR2	73	RW	RDI0LT0	B3	RW		F3
	34			74		RDI0LT1	B4	RW		F4
	35			75		RDI0RO0	B5	RW		F5
	36		ACE01CR1	76	RW	RDI0RO1	B6	RW		F6
	37		ACE01CR2	77	RW		B7		CPU_F	F7	RL
	38			78			B8			F8
	39			79			B9			F9
	3A			7A			BA		FLS_PR1	FA	RW
	3B			7B			BB			FB
	3C			7C			BC			FC
	3D			7D			BD		DAC_CR	FD	RW
	3E			7E			BE		CPU_SCR1	FE	#
	3F			7F			BF		CPU_SCR0	FF	#
Blank fields are	Reserved and must not be accessed.					# Access is bit specific.

Document Number: 38-12025 Rev. *O Page 17 of 45

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