Cypress CY8C21434, CY8C21334, CY8C21634, CY8C21234, CY8C21534 manual Pin Information, Pin Part Pinout

CY8C21634, CY8C21534

CY8C21434, CY8C21334, CY8C21234

Pin Information

The CY8C21x34 PSoC device is available in a variety of packages which are listed in the following tables. Every port pin (labeled with a “P”) is capable of Digital IO and connection to the common analog bus. However, Vss, Vdd, SMP, and XRES are not capable of Digital IO.

16-Pin Part Pinout

Figure 3. CY8C21234 16-Pin PSoC Device

A, I,M, P0[7] A, I,M, P0[5] A, I,M, P0[3] A, I,M, P0[1]

SMP

Vss M,I2CSCL,P1[1] Vss

116 Vdd

215 P0[6], A,I, M

314 P0[4], A,I, M

4	SOIC	13	P0[2], A,I, M
			P0[0], A,I, M
5		12
6		11	P1[4],EXTCLK,M
7		10	P1[2],M
8		9	P1[0],I2C SDA,M

Table 3. Pin Definitions - CY8C21234 16-Pin (SOIC)

Pin No.		Type		Name	Description
	Digital		Analog
1	IO		I, M	P0[7]	Analog column mux input.
2	IO		I, M	P0[5]	Analog column mux input.
3	IO		I, M	P0[3]	Analog column mux input, integrating input.
4	IO		I, M	P0[1]	Analog column mux input, integrating input.
5	Power			SMP	Switch Mode Pump (SMP) connection to required external components.
6	Power			Vss	Ground connection.
7	IO		M	P1[1]	I2C Serial Clock (SCL), ISSP-SCLK[3].
8	Power			Vss	Ground connection.
9	IO		M	P1[0]	I2C Serial Data (SDA), ISSP-SDATA[3]..
10	IO		M	P1[2]
11	IO		M	P1[4]	Optional External Clock Input (EXTCLK).
12	IO		I, M	P0[0]	Analog column mux input.
13	IO		I, M	P0[2]	Analog column mux input.
14	IO		I, M	P0[4]	Analog column mux input.
15	IO		I, M	P0[6]	Analog column mux input.
16	Power			Vdd	Supply voltage.

LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input.

Note

3. These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Programmable System-on-Chip Technical Reference Manual for details.

Document Number: 38-12025 Rev. *O Page 8 of 45

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