Dell M610 manual Delivering Intelligent Performance, Chipset Overview / Description

Dell™ PowerEdge™ M610 Technical Guidebook

Section 7. Chipset

A. Overview / Description

The PowerEdge M610 planar incorporated the Intel 5520 chipset (code named Tylersburg) for I/O and processor interfacing. Tylersburg is designed to support Intel's 5500 series processors (code named Nehalem-EP), QPI interconnect, DDR3 memory technology, and PCI Express Generation 2. The Tylersburg chipset consists of the Tylersburg-36D IOH and ICH9.

Delivering Intelligent Performance

Next Generation Intel® Microarchitecture

Bandwidth Intensive

Intel® QuickPath Technology

Integrated Memory Controller

Threaded Applications

45nm Quad-Core Intel® Xeon® processors Intel® Hyper-Threading Technology Controller

Performance On Demand

Intel® Turbo Boost Technology

Intel® Intelligent Power Technology

Performance that adapts to your software environment

The Intel 5520 chipset (code named Tylersburg) I/O Hub (IOH)

The planar uses the The Intel® 5520 chipset (code named Tylersburg) I/O Hub (IOH)-36D IOH to provide a link between the 5500 series 2S processor (Nehalem EP) and I/O components. The main components of the IOH consist of two full-width QuickPath Interconnect links (one to each processor), 36 lanes of PCI Express Gen2, a x4 Direct Media Interface (DMI), and an integrated IOxAPIC.

IOH QuickPath Interconnect (QPI)

The QuickPath Architecture consists of serial point-to-point interconnects for the processors and the IOH. The PowerEdge T610 has a total of three QuickPath Interconnect (QPI) links: one link connecting the processors and links connecting both processors with the IOH. Each link consists of 20 lanes (full-width) in each direction with a link speed of up to 6.4 GT/s. An additional lane is reserved for a forwarded clock. Data is sent over the QPI links as packets.

The QuickPath Architecture implemented in the IOH and CPUs features four layers. The Physical layer consists of the actual connection between components. It supports Polarity Inversion and Lane Reversal for optimizing component placement and routing. The Link layer is responsible for flow control and the reliable transmission of data. The Routing layer is responsible for the routing of QPI data packets. Finally, the Protocol layer is responsible for high-level protocol communications, including the implementation of a MESIF (Modify, Exclusive, Shared, Invalid, Forward) cache coherence protocol.

Intel Direct Media Interface (DMI)

The DMI (previously called the Enterprise Southbridge Interface) connects the Tylersburg IOH with the Intel I/O Controller Hub (ICH). The DMI is equivalent to a x4 PCIe Gen1 link with a transfer rate of 1 Gb/s in each direction.

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