2: Programmer’s Model
2-12 EPSON ARM720T CORE CPU MANUAL
2.8.4 Fast interrupt request
The FIQ exception is used for most performance-critical interrupts in a system. In ARM state
the processor has sufficient private registers to remove the necessity for register saving,
minimizing the overhead of context switching.
FIQ is externally generated by taking the nFIQ input LOW. nFIQ and nIRQ are considered
asynchronous, and a cycle delay for synchronization is incurred before the interrupt can affect
the processor flow.
Irrespective of whether the exception was entered from ARM or Thumb state, a FIQ handler
must leave the interrupt by executing:
SUBS PC, r14_fiq, #4
FIQ can be disabled by setting the F flag in the CPSR.
Note: This is not possible from User mode.
If the F flag is clear, the ARM720T processor checks for a LOW level on the output of the FIQ
synchronizer at the end of each instruction.
2.8.5 Interrupt request
The IRQ exception is a normal interrupt caused by a LOW level on the nIRQ input. IRQ has
a lower priority than FIQ and is masked out when a FIQ sequence is entered. It can be
disabled at any time by setting the I bit in the CPSR, though this can only be done from a
privileged (non-User) mode.
Irrespective of whether the exception was entered from ARM or Thumb state, an IRQ handler
must return from the interrupt by executing:
SUBS PC, r14_irq, #4
2.8.6 Abort
An abort indicates that the current memory access cannot be completed. It can be signaled
either by the protection unit, or by the HRESP bus. The ARM720T processor checks for the
abort exception during memory access cycles.
There are two types of abort, as follows:
Prefetch Abort This occurs during an instruction prefetch. The prefetched
instruction is marked as invalid, but the exception is not taken
until the instruction reaches the head of the pipeline. If the
instruction is not executed, for example because a branch occurs
while it is in the pipeline, the abort does not take place.
Data Abort This occurs during a data access. The action taken depends on the
instruction type:
• Single data transfer instructions (LDR, STR) write-back
modified base registers. The Abort handler must be aware of
this.
• The swap instruction (SWP) is aborted as though it had not
been executed.
• Block data transfer instructions (LDM, STM) complete. If
write-back is set, the base is updated. If the instruction
attempts to overwrite the base with data (that is, it has the
base in the transfer list), the overwriting is prevented. All
register overwriting is prevented after an abort is indicated.
This means, in particular, that r15 (always the last register to
be transferred) is preserved in an aborted LDM instruction.