9: Debugging Your System
9-28 EPSON ARM720T CORE CPU MANUAL
All these instructions execute at debug speed. Debug speed is much slower than system speed.
This is because between each core clock, 33 clocks occur in order to shift in an instruction, or
shift out data. Executing instructions this slowly is acceptable for accessing the core state
because the ARM720T processor is fully static. However, you cannot use this method for
determining the state of the rest of the system.
While in debug state, only the following instructions can be scanned into the instruction
pipeline for execution:
• all data processing operations
• all load, store, load multiple, and store multiple instructions
• MSR and MRS.
9.16.2 Determining system state
To meet the dynamic timing requirements of the memory system, any attempt to access
system state must occur with the clock qualified by HCLKEN. To perform a memory access,
HCLKEN must be used to force the ARM720T processor to run in normal operating mode. This
is controlled by bit 33 of scan chain 1.
An instruction placed in scan chain 1 with bit 33, the DBGBREAK bit, LOW executes at debug
speed. To execute an instruction at system speed, the instruction prior to it must be scanned
into scan chain 1 with bit 33 set HIGH.
After the system speed instruction has scanned into the data bus and clocked into the pipeline,
the RESTART instruction must be loaded into the TAP controller. RESTART causes the
ARM720T processor to:
1 Switch automatically to HCLKEN control.
2 Execute the instruction at system speed.
3 Reenter debug state.
When the instruction has completed, DBGACK is HIGH and the core reverts to DBGTCKEN
control. It is now possible to select INTEST in the TAP controller and resume debugging.
The debugger must look at both DBGACK and HTRANS[1:0] to determine whether a system
speed instruction has completed. To access memory, the ARM720T core drives both bits of
HTRANS[1:0] LOW after it has synchronized back to system speed. This transition is used by
the memory controller to arbitrate whether the ARM720T core can have the bus in the next
cycle. If the bus is not available, the ARM720T processor might have its clock stalled
indefinitely. The only way to determine whether the memory access has completed is to
examine the state of both HTRANS[1:0] and DBGACK. When both are HIGH, the access has
completed.
The debugger usually uses EmbeddedICE-RT to control debugging, and so the state of
HTRANS[1:0] and DBGACK can be determined by reading the EmbeddedICE-RT status
register. See
Debug status register
on page 9-41 for more details.
The state of the system memory can be fed back to the debug host by using system speed load
multiples and debug speed store multiples.
There are restrictions on which instructions can have bit 33 set. The valid instructions on
which to set this bit are:
•loads
•stores
• load multiple
• store multiple.
See also

Exit from debug state

on page 9-29.