45
Users Manual
Event Status and Event Status Enable Registers
The Event Status Register (ESR) assigns specified events to specific bits (see Figure
The Event Status Enable Register (ESE) is a mask register that allows the host to enable or disable (mask) each bit in the ESR. When a bit in the ESE is 1, the corresponding bit in the ESR is enabled. When any enabled bit in the ESR changes from O to 1, the ESB bit in the Status Byte Register also goes to 1. When the ESR is read (using the *ESR? com- mand) or cleared (using the *CLS command), the ESB bit in the Status Byte Register returns to 0.
Logical OR
Power On | User Request | Command Error | Execution Error | Device Dependent Error | Query Error | Request Control | Operation Complete |
7 6 5 4 3 2 1 0
&
&
&
& & &
& &
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Standard
Event Status Register
*ESR?
Standard
Event Status Enable
Register
*ESE *ESE?
Summary Message
Event Summary Bit (ESB)
(Bit 5 of Status Byte Register)
aam22f.eps
Figure
Figure
permission of the IEEE Standards Department.