5.2.1 | I/O registers | 5 | - 6 |
5.2.2 | Command block registers | 5 | - 8 |
5.2.3 | Control block registers | 5 | - 13 |
5.3 | Host Commands | 5 | - 13 |
5.3.1 | Command code and parameters | 5 | - 14 |
5.3.2 | Command descriptions | 5 | - 16 |
5.3.3 | Error posting | 5 | - 66 |
5.4 | Command Protocol | 5 | - 67 |
5.4.1 | Data transferring commands from device to host | 5 | - 67 |
5.4.2 | Data transferring commands from host to device | 5 | - 69 |
5.4.3 | Commands without data transfer | 5 | - 71 |
5.4.4 | Other commands | 5 | - 72 |
5.4.5 | DMA data transfer commands | 5 | - 72 |
5.5 | Ultra DMA feature set | 5 | - 74 |
5.5.1 | Overview | 5 | - 74 |
5.5.2 | Phases of operation | 5 | - 75 |
5.5.3 | Ultra DMA data in commands | 5 | - 75 |
5.5.3.1 | Initiating an Ultra DMA data in burst | 5 | - 75 |
5.5.3.2 | The data in transfer | 5 | - 76 |
5.5.3.3 | Pausing an Ultra DMA data in burst | 5 | - 76 |
5.5.3.4 | Terminating an Ultra DMA data in burst | 5 | - 77 |
5.5.4 | Ultra DMA data out commands | 5 | - 79 |
5.5.4.1 | Initiating an Ultra DMA data out burst | 5 | - 79 |
5.5.4.2 | The data out transfer | 5 | - 80 |
5.5.4.3 | Pausing an Ultra DMA data out burst | 5 | - 80 |
5.5.4.4 | Terminating an Ultra DMA data out burst | 5 | - 81 |
5.5.5 | Ultra DMA CRC rules | 5 | - 83 |
5.5.6 | Series termination required for Ultra DMA | 5 | - 84 |
5.6 | Timing | 5 | - 85 |
5.6.1 | PIO data transfer | 5 | - 85 |
5.6.2 | Multiword data transfer | 5 | - 86 |
5.6.3 | Ultra DMA data transfer | 5 | - 87 |
5.6.3.1 | Initiating an Ultra DMA data in burst | 5 | - 87 |
5.6.3.2 | Ultra DMA data burst timing requirements | 5 | - 88 |
5.6.3.3 | Sustained Ultra DMA data in burst | 5 | - 90 |
5.6.3.4 | Host pausing an Ultra DMA data in burst | 5 | - 91 |
ix |
