Fujitsu FR81 6.2.4 Register designated Field

CM71-00105-1E FUJITSU MICROELECTRONICS LIMITED 91
FR81 Family CHAPTER 6 INSTRUCTION OVERVIEW
6.2
TYPE-N
It has 14-bit OP Code (OP) and floating point register list (frlist). These are the instruction formats
that have been added to FR81 Family CPU.
6.2.4 Register designated Field
●General-purpose register designated Field (Ri/Rj)
Among Instruction formats, fields that designate general-purpose register are 4-bit length Ri and Rj.
Relation between bit pattern of general purpose register and register designated field has been indicated in
Table 6.2-1.
Table 6.2-1 Bit pattern of general purpose register and register designated field
MSB LSB
(n+0) OP -
(n+2) frlist
Ri / Rj Register Ri / Rj Register
0000BR0 1000BR8
0001BR1 1001BR9
0010BR2 1010BR10
0011BR3 1011BR11
0100BR4 1100BR12
0101BR5 1101BR13
0110BR6 1110BR14
0111BR7 1111BR15