FR81 Family
444 FUJITSU MICROELECTRONICS LIMITED CM71-00105-1E
APPENDIX
APPENDIX A Instruction Lists
Table A.2-16 FPU Memory Load Instructions (7 Instructions)
• The field o14 and u14 in TYPE-L instruction format have the following relation to the values disp16,
udisp16 in assembly notation.
o14 = disp16 >> 2
u14 = udisp16 >> 2
• The field u16 in TYPE-J instruction format has the following relation to the value udisp18 in assembly
notation.
u16 = udisp18 >> 2
Table A.2-17 FPU Memory Store Instructions (7 Instructions)
• The field o14 and u14 in TYPE-L instruction format have the following relation to the values disp16 and
udisp16 in assembly notation.
o14 = disp16 >> 2
u14 = udisp16 >> 2
• The field u16 in TYPE-J instruction format has the following relation to the value udisp18 in assembly
notation.
u16 = udisp18 >> 2
Mnemonic Format OP CYC FCC
ELGU RMW Operation Remarks Reference
FLD @Rj, FRi K 07-C a ---- - (Rj) → FRi Word 7. 70
FLD @(R13, Rj), FRi K 07-E a ---- - (R13+Rj) → FRi Word 7. 71
FLD @(R14, disp16), FRi L 07-D0 a ---- - (R14+o14 × 4) → FRi Word 7. 72
FLD @(R15, udisp16), FRi L 07-D4 a ---- - (R15+u14 × 4) → FRi Word 7.73
FLD @R15+, FRi L 07-D8 a ---- - (R15) → FRi
R15 + 4 → R15 Word 7. 74
FLD @(BP, udisp18), FRi J 07-7 a ---- - (BP+u16 × 4) → FRi Wo rd 7.75
FLDM (frlist) N 07-DC *1 ---- - for FRi of frlist
(R15) → FRi
R15 + 4 → R15
Load Multiple
FR0 to FR15 7.76
*1: The number of execution cycles for FLDM instruction is a × n when "n" is the number of registers designated.
Mnemonic Format OP CYC FCC
ELGU RMW Operation Remarks Reference
FST FRi, @Rj K 17-C a ---- - FRi → (Rj) Wo rd 7.83
FST FRi, @(R13, Rj) K 17-E a ---- - FRi → (R13+Rj) Wo rd 7.84
FST FRi, @(R14, disp16) L 17-D0 a ---- - FRi → (R14+o14 × 4) Wor d 7.85
FST FRi, @(R15, udisp16) L 17-D4 a ---- - FRi → (R15+u14 × 4) Wor d 7.86
FST FRi, @-R15 L 17-D8 a ---- - R15 - 4 → R15
FRi → (R15) Wor d 7.87
FST FRi, @(BP, udisp18) J 17 -7 a ---- - FRi → (BP+u16 × 4) Wor d 7.8 8
FSTM (frlist) N 17-DC *1 ---- - for FRi of frlist
R15 - 4 → R15
FRi → (R15)
Store Multiple
FR0 to FR15 7.89
*1: The number of execution cycles for FSTM instruction is a × n when "n" is the number of registers designated.