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Fujitsu FR81 manual - page 2

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Main Page Page Page PREFACE Objectives and targeted reader Organization of this Manual ii Copyright 2009 FUJITSU MICROELECTRONICS LIMITED All rights reserved. CONTENTS Page CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS .............................................. 103 Page Page Page Page Page Page 1.1 Features of FR81 Family CPU FR81 Family 1.2 Changes from the earlier FR Family Page Page Page 2.1 Address Space The address space of FR81 Family CPU is 32 bits (4Gbyte). 2.1.1 Direct Address Area CM71-00105-1E FUJITSU MICROELECTRONICS LIMITED 9 2.1.2 Vector Table Area Page 2.1.3 20-bit Addressing Area & 32-bit Addressing Area 2.2 Data Structure 2.2.1 Byte Data 2.2.2 Half Word Data 2.2.3 Word Data 2.2.4 Byte Order 2.3 Word Alignment The data type used determines restrictions on the designation of memory addresses (word alignment). 2.3.1 Program Access 2.3.2 Data Access Page Page 3.2 General-purpose Registers 3.2.1 Configuration of General-purpose Registers 3.2.2 Special Usage of General-purpose Registers 3.2.3 Relation between Stack Pointer and R15 3.3 Dedicated Registers FR81 Family CPU has dedicated registers reserved for special usages. 3.3.1 Configuration of Dedicated Registers 3.3.2 Program Counter (PC) 3.3.3 Program Status (PS) 3.3.4 System Status Register (SSR) 0011 MPUFPUUMDBG 3.3.5 Interrupt Level Mask Register (ILM) bit20 bit19 bit18 bit17 bit16 ILM4 ILM3 ILM2 ILM1 ILM0 01111 3.3.6 Condition Code Register (CCR) CCR ReservedReserved SINZVC --00XXXX Page 3.3.7 System Condition Code Register (SCR) 3.3.8 Return Pointer (RP) 3.3.9 System Stack Pointer (SSP) 3.3.10 User Stack Pointer (USP) CM71-00105-1E FUJITSU MICROELECTRONICS LIMITED 29 CHAPTER 3 PROGRAMMING MODEL 3.3 Figure 3.3-15 Example of User Stack Pointer (USP) Operation 3.3.11 Table Base Register (TBR) 3.3.12 Multiplication/Division Register (MDH, MDL) Page 3.3.13 Base Pointer (BP) 3.3.14 FPU Control Register (FCR) XXXX Floating point condition code (FCC) FCC Reserved RM EEF ECF CEF Rounding mode (RM) bit19 bit18 RM1 RM0 XX Floating point exception enable flag (EEF) bit15 bit14bit17 bit16 bit13bit12 Floating point exception accumulative flag (ECF) bit9 bit8bit11 bit10 bit7 bit6 Floating point exception flag (CFE) bit3bit2bit5 bit4 bit1 bit0 3.3.15 Exception status register (ESR) Register List (RL) RL Reserved INV bit31bit16 RL15 RL0 0000 Invalid instruction exception source (INV) bit0 PIFPUIF 0000000 bit6 DT SPR DSRI Page 3.4 Floating-point Register Floating point registers are using that store results for floating point calculations. Page 4.1 Reset 4.2 Basic Operations in EIT Processing 4.2.1 Types of EIT Processing and Prior Preparation 4.2.2 EIT Processing Sequence 4.2.3 Recovery from EIT Processing 4.3 Processor Operation Status Page 4.4 Exception Processing 4.4.1 Invalid Instruction Exception 4.4.2 Instruction Access Protection Violation Exception 4.4.3 Data Access Protection Violation Exception 4.4.4 FPU Exception 4.4.5 Instruction Break 4.4.6 Guarded Access Break 4.5 Interrupts 4.5.1 General interrupts Page 4.5.2 Non-maskable Interrupts (NMI) 4.5.3 Break Interrupt 4.5.4 Data Access Error Interrupt 4.6 Traps 4.6.1 INT Instructions 4.6.2 INTE Instruction 4.6.3 Step Trace Traps Page 4.7 Multiple EIT processing and Priority Levels 4.7.1 Multiple EIT Processing 4.7.2 Priority Levels of EIT Requests 4.7.3 EIT Acceptance when Branching Instruction is Executed 4.8 Timing When Register Settings Are Reflected 4.8.1 Timing when the interrupt enable flag (I) is requested 4.8.2 Timing of Reflection of Interrupt Level Mask Register (ILM) 4.9 Usage Sequence of General Interrupts 4.9.1 Preparation while using general interrupts 4.9.2 Processing during an Interrupt Processing Routine 4.9.3 Points of Caution while using General Interrupts Page Page Page 5.1 Instruction execution based on Pipeline 5.1.1 Integer Pipeline (Example 1) (Example 2) 5.1.2 Floating Point Pipeline 5.2 Pipeline Operation and Interrupt Processing 5.2.1 Mismatch in Acceptance and Cancellation of Interrupt 5.2.2 Method of preventing the mismatched pipeline conditions 5.3 Pipeline hazards 5.3.1 Occurrence of data hazard 5.3.2 Register Bypassing 5.3.3 Interlocking 5.3.4 Interlocking produced by reference to R15 after Changing the Stack flag (S) 5.3.5 Structural Hazard 5.3.6 Control Hazard 5.4 Non-block loading 5.5 Delayed branching processing 5.5.1 Example of branching with non-delayed branching instructions (Branching conditions not satisfied) 5.5.2 Example of processing of delayed branching instruction Page Page 6.1 Instruction System 6.1.1 Integer Type Instructions Page 6.1.2 Floating Point Type Instructions 6.2 Instructions Formats This part describes about Instruction Formats of FR81 Family CPU. 6.2.1 Instructions Notation Formats 6.2.2 Addressing Formats 6.2.3 Instruction Formats Page Page Page 6.2.4 Register designated Field Page 6.3 Data Format 6.3.1 Data Format Used by Integer Type Instructions (Common with All FR Family) 6.3.2 Format Used for Floating Point Type Instructions Page 6.4 Read-Modify-Write type Instructions 6.5 Branching Instructions and Delay Slot 6.5.1 Delayed Branching Instructions 6.5.2 Specific example of Delayed Branching Instructions 6.5.3 Non-Delayed Branching Instructions 6.6 Step Division Instructions 6.6.1 Signed Division 6.6.2 Unsigned Division Page Page Page 7.1 ADD (Add 4bit Immediate Data to Destination Register) Befo re e xec ution After execution 7.2 ADD (Add Word Data of Source Register to Destination Page 7.3 ADD2 (Add 4bit Immediate Data to Destination Register) Page 7.4 ADDC (Add Word Data of Source Register and Carry Bit to Page 7.5 ADDN (Add Immediate Data to Destination Register) Page 7.6 ADDN (Add Word Data of Source Register to Destination Page 7.7 ADDN2 (Add Immediate Data to Destination Register) Page 7.8 ADDSP (Add Stack Pointer and Immediate Data) Page 7.9 AND (And Word Data of Source Register to Data in Page 7.10 AND (And Word Data of Source Register to Destination Befor e e x ec ution After execution 7.11 ANDB (And Byte Data of Source Register to Data in Page 7.12 ANDCCR (And Condition Code Register and Immediate Data) Page 7.13 ANDH (And Halfword Data of Source Register to Data in Page 7.14 ASR (Arithmetic shift to the Right Direction) Page 7.15 ASR (Arithmetic shift to the Right Direction) Page 7.16 ASR2 (Arithmetic shift to the Right Direction) Page 7.17 BANDH (And 4bit Immediate Data to Higher 4bit of Byte Page 7.18 BANDL (And 4bit Immediate Data to Lower 4bit of Byte Page 7.19 Bcc (Branch relative if Condition satisfied) Page 7.20 Bcc:D (Branch relative if Condition satisfied) Page 7.21 BEORH (Eor 4bit Immediate Data to Higher 4bit of Byte Page 7.22 BEORL (Eor 4bit Immediate Data to Lower 4bit of Byte Data Page 7.23 BORH (Or 4bit Immediate Data to Higher 4bit of Byte Data Before exec ution After execution 7.24 BORL (Or 4bit Immediate Data to Lower 4bit of Byte Data in Page 7.25 BTSTH (Test Higher 4bit of Byte Data in Memory) Page 7.26 BTSTL (Test Lower 4bit of Byte Data in Memory) Page 7.27 CALL (Call Subroutine) Page 7.28 CALL (Call Subroutine) Page 7.29 CALL:D (Call Subroutine) Before execution of CALL instruction After branching 7.30 CALL:D (Call Subroutine) Before execution of CALL instruction After branching 7.31 CMP (Compare Immediate Data and Destination Register) Page 7.32 CMP (Compare Word Data in Source Register and Page 7.33 CMP2 (Compare Immediate Data and Destination Register) Page 7.34 DIV0S (Initial Setting Up for Signed Division) Page 7.35 DIV0U (Initial Setting Up for Unsigned Division) Page 7.36 DIV1 (Main Process of Division) This is a step division instruction used for unsigned division. Page 7.37 DIV2 (Correction When Remain is zero) Page 7.38 DIV3 (Correction When Remain is zero) Page 7.39 DIV4S (Correction Answer for Signed Division) Page 7.40 DMOV (Move Word Data from Direct Address to Register) 184 FUJITSU MICROELECTRONICS LIMITED CM71-00105-1E 7.40 DMOV @88H, R13 ; Bit pattern of the instruction: 0000 1000 0010 0010 7.41 DMOV (Move Word Data from Register to Direct Address) 186 FUJITSU MICROELECTRONICS LIMITED CM71-00105-1E 7.41 DMOV R13,@54H ; Bit pattern of the instruction: 0001 1000 0001 0101 50 7.42 DMOV (Move Word Data from Direct Address to Post Page 7.43 DMOV (Move Word Data from Post Increment Register Page 7.44 DMOV (Move Word Data from Direct Address to Pre Decrement Register Indirect Address) Page 7.45 DMOV (Move Word Data from Post Increment Register Page 7.46 DMOVB (Move Byte Data from Direct Address to Register) Page 7.47 DMOVB (Move Byte Data from Register to Direct Address) Page 7.48 DMOVB (Move Byte Data from Direct Address to Post Page 7.49 DMOVB (Move Byte Data from Post Increment Register Page 7.50 DMOVH (Move Halfword Data from Direct Address to Page 7.51 DMOVH (Move Halfword Data from Register to Direct Address) Page 7.52 DMOVH (Move Halfword Data from Direct Address to Post Page 7.53 DMOVH (Move Halfword Data from Post Increment Register Indirect Address to Direct Address) Page 7.54 ENTER (Enter Function) 212 FUJITSU MICROELECTRONICS LIMITED CM71-00105-1E 7.54 ENTER #0CH ; Bit pattern of the instruction: 0000 1111 0000 0011 7.55 EOR (Exclusive Or Word Data of Source Register to Data in Page 7.56 EOR (Exclusive Or Word Data of Source Register to Page 7.57 EORB (Exclusive Or Byte Data of Source Register to Data Page 7.58 EORH (Exclusive Or Halfword Data of Source Register to Page 7.59 EXTSB (Sign Extend from Byte Data to Word Data) Page 7.60 EXTSH (Sign Extend from Byte Data to Word Data) Page 7.61 EXTUB (Unsign Extend from Byte Data to Word Data) Page 7.62 EXTUH (Unsign Extend from Byte Data to Word Data) Page 7.63 FABSs (Single Precision Floating Point Absolute Value) 7.64 FADDs (Single Precision Floating Point Add) Page 7.65 FBcc (Floating Point Conditional Branch) Page 7.66 FBcc:D (Floating Point Conditional Branch with Delay Slot) Page 7.67 FCMPs (Single Precision Floating Point Compare) Page 7.68 FDIVs (Single Precision Floating Point Division) Page 7.69 FiTOs (Convert from Integer to Single Precision Floating Point) Page 7.70 FLD (Single Precision Floating Point Data Load) 7.71 FLD (Single Precision Floating Point Data Load) 7.72 FLD (Single Precision Floating Point Data Load) 7.73 FLD (Single Precision Floating Point Data Load) 7.74 FLD (Single Precision Floating Point Data Load) 7.75 FLD (Load Word Data in Memory to Floating Register) 7.76 FLDM (Single Precision Floating Point Data Load to Multiple Register) Page 7.77 FMADDs (Single Precision Floating Point Multiply and Add) Page 7.78 FMOVs (Single Precision Floating Point Move) 7.79 FMSUBs (Single Precision Floating Point Multiply and Subtract) Page 7.80 FMULs (Single Precision Floating Point Multiply) Page 7.81 FNEGs (Single Precision Floating Point sign reverse) 7.82 FSQRTs (Single Precision Floating Point Square Root) 7.83 FST (Single Precision Floating Point Data Store) 7.84 FST (Single Precision Floating Point Data Store) 7.85 FST (Single Precision Floating Point Data Store) 7.86 FST (Single Precision Floating Point Data Store) 7.87 FST (Single Precision Floating Point Data Store) 7.88 FST (Store Word Data in Floating Point Register to 7.89 FSTM (Single Precision Floating Point Data Store from Multiple Register) Page 7.90 FsTOi (Convert from Single Precision Floating Point to Integer) Page 7.91 FSUBs (Single Precision Floating Point Subtract) Page 7.92 INT (Software Interrupt) 272 FUJITSU MICROELECTRONICS LIMITED CM71-00105-1E 7.92 INT #20H ; Bit pattern of the instruction: 0001 1111 0010 0000 1+3a cycles MSB LSB 00011111 u8 7.93 INTE (Software Interrupt for Emulator) 274 FUJITSU MICROELECTRONICS LIMITED CM71-00105-1E 7.93 INTE ; Bit pattern of the instruction: 1001 1111 0011 0000 1+3a cycles MSB LSB 1001111100110000 7.94 JMP (Jump) Page 7.95 JMP:D (Jump) Before execution of JMP instruction After branching 7.96 LCALL (Long Call Subroutine) 7.97 LCALL:D (Long Call Subroutine) 7.98 LD (Load Word Data in Memory to Register) Page 7.99 LD (Load Word Data in Memory to Register) Page 7.100 LD (Load Word Data in Memory to Register) Page 7.101 LD (Load Word Data in Memory to Register) Page 7.102 LD (Load Word Data in Memory to Register) Page 7.103 LD (Load Word Data in Memory to Register) 7.104 LD (Load Word Data in Memory to Register) Page 7.105 LD (Load Word Data in Memory to Program Status Page 7.106 LDI:20 (Load Immediate 20bit Data to Destination Register) Page 7.107 LDI:32 (Load Immediate 32 bit Data to Destination Page 7.108 LDI:8 (Load Immediate 8bit Data to Destination Register) Page 7.109 LDM0 (Load Multiple Registers) Page 7.110 LDM1 (Load Multiple Registers) Page 7.111 LDUB (Load Byte Data in Memory to Register) Page 7.112 LDUB (Load Byte Data in Memory to Register) Page 7.113 LDUB (Load Byte Data in Memory to Register) Page 7.114 LDUB (Load Byte Data in Memory to Register) 7.115 LDUH (Load Halfword Data in Memory to Register) Page 7.116 LDUH (Load Halfword Data in Memory to Register) Page 7.117 LDUH (Load Halfword Data in Memory to Register) Page 7.118 LDUH (Load Halfword Data in Memory to Register) 7.119 LEAVE (Leave Function) CM71-00105-1E FUJITSU MICROELECTRONICS LIMITED 321 7.119 LEAVE ; Bit pattern of the instruction: 1001 1111 1001 0000 7.120 LSL (Logical Shift to the Left Direction) Page 7.121 LSL (Logical Shift to the Left Direction) Before execution Aft er execution 7.122 LSL2 (Logical Shift to the Left Direction) Page 7.123 LSR (Logical Shift to the Right Direction) Page 7.124 LSR (Logical Shift to the Right Direction) Page 7.125 LSR2 (Logical Shift to the Right Direction) Page 7.126 MOV (Move Word Data in Source Register to Destination Page 7.127 MOV (Move Word Data in Source Register to Destination Page 7.128 MOV (Move Word Data in Program Status Register to Page 7.129 MOV (Move Word Data in Source Register to Destination Page 7.130 MOV (Move Word Data in Source Register to Program Status Register) Page 7.131 MOV (Move Word Data in General Purpose Register to Floating Point Register) 7.132 MOV (Move Word Data in Floating Point Register to General Purpose Register) 7.133 MUL (Multiply Word Data) Page 7.134 MULH (Multiply Halfword Data) Page 7.135 MULU (Multiply Unsigned Word Data) Page 7.136 MULUH (Multiply Unsigned Halfword Data) Page 7.137 NOP (No Operation) Page 7.138 OR (Or Word Data of Source Register to Data in Memory) Page 7.139 OR (Or Word Data of Source Register to Destination Page 7.140 ORB (Or Byte Data of Source Register to Data in Memory) Page 7.141 ORCCR (Or Condition Code Register and Immediate Data) Page 7.142 ORH (Or Halfword Data of Source Register to Data in Page 7.143 RET (Return from Subroutine) Page 7.144 RET:D (Return from Subroutine) Before execution of RET instruction After branching 7.145 RETI (Return from Interrupt) Page 372 FUJITSU MICROELECTRONICS LIMITED CM71-00105-1E 7.145 RETI ; Bit pattern of the instruction: 1001 0111 0011 0000 7.146 SRCH0 (Search First Zero bit position distance From MSB) Page 7.147 SRCH1 (Search First One bit position distance From MSB) Page 7.148 SRCHC (Search First bit value change position distance From MSB) Page 7.149 ST (Store Word Data in Register to Memory) Page 7.150 ST (Store Word Data in Register to Memory) Page 7.151 ST (Store Word Data in Register to Memory) Page 7.152 ST (Store Word Data in Register to Memory) Page 7.153 ST (Store Word Data in Register to Memory) Before exec ution After execution 7.154 ST (Store Word Data in Register to Memory) 7.155 ST (Store Word Data in Register to Memory) Page 7.156 ST (Store Word Data in Program Status Register to Page 7.157 STB (Store Byte Data in Register to Memory) Page 7.158 STB (Store Byte Data in Register to Memory) Page 7.159 STB (Store Byte Data in Register to Memory) Page 7.160 STB (Store Byte Data in Register to Memory) 7.161 STH (Store Halfword Data in Register to Memory) Page 7.162 STH (Store Halfword Data in Register to Memory) Page 7.163 STH (Store Halfword Data in Register to Memory) Page 7.164 STH (Store Halfword Data in Register to Memory) 7.165 STILM (Set Immediate Data to Interrupt Level Mask Page 7.166 STM0 (Store Multiple Registers) Before ex ecution After execution 7.167 STM1 (Store Multiple Registers) Page 7.168 SUB (Subtract Word Data in Source Register from Page 7.169 SUBC (Subtract Word Data in Source Register and Carry bit from Destination Register) Page 7.170 SUBN (Subtract Word Data in Source Register from Page 7.171 XCHB (Exchange Byte Data) Page Page Page Page A.1 Meaning of Symbols A.1.1 Mnemonic and Operation Columns Page Page Page Page A.1.2 Operation Column A.1.3 Format Column A.1.4 OP Column A.1.5 CYC Column A.1.6 FLAG Column A.1.7 RMW Column A.1.8 Reference Column A.2 Instruction Lists This part indicates Instruction Lists of FR81 Family CPU. Page Page Page Page Page Page Page Page Page Page Page Page Page A.3 List of Instructions that can be positioned in the Delay Slot Page Page CM71-00105-1E FUJITSU MICROELECTRONICS LIMITED 451 APPENDIX B Instruction Maps B.1 Instruction Maps The following shows an instruction map when the operation code consists of 8 or less bits. Higher 4 bits Lowe r 4 bits B.2 Extension Instruction Maps The following shows an instruction map when the operation code consists of 12 or more bits. Page Page Page C.2 FPU Exceptions Page C.3 Round Processing Page Page Page Index