Fujitsu FR81 - page 24

FR81 Family
10 FUJITSU MICROELECTRONICS LIMITED CM71-00105-1E
CHAPTER 2 MEMORY ARCHITECTURE
2.1
As a result of reset, the value of Table Base Register (TBR) is initialized to 000F FC00H, and the range of
vector table area extends from 000F FC00H to 000F FFFFH. By rewriting the Table Base Register (TBR),
the vector table area can be allocated to any desired location.
A vector table is composed of entry addresses for each EIT processing programs. Each vector table
contains values whose use is fixed according to the CPU architecture, and values that vary according to the
type of built-in peripheral functions. The structure of vector table area is shown in Table 2.1-1.
Table 2.1-1 Structure of Vector Table Area
For vector tables of actual models, refer to the hardware manuals for each model.
Offset from
TBR Vecto r number Model- dependence EIT value description Remarks
3FCH00HNo reset
3F8H01HNo system reserved
3F4H02HNo system reserved Disabled
3F0H03HNo system reserved Disabled
3ECH04HNo system reserved Disabled
3E8H05HNo FPU exception
3E4H06HNo Instruction access protection
violation exception
3E0H07HNo Data access protection
violation exception
3DCH08HNo Data access error interrupt
3D8H09HNo INTE instruction For use in the emulator
3D4H0AHNo Instruction break
3D0H0BHNo system reserved
3CCH0CHNo Step trace trap
3C8H0DHNo system reserved
3C4H0EHNo Invalid instruction exception
3C0H0FHNo NMI request
3BCH
to
304H
0FH
to
3EH
Yes
General interrupt
(used in external interrupt,
interrupt from peripheral
function)
Refer to the Hardware Manual for each
model
300H3FHNo General interrupts Used in Delayed interrupt
2FCH40HNo system reserved Used in REALOS
2F8H41HNo system reserved Used in REALOS
2F4H
to
000H
42H
to
FFH
No Used in INT instruction