Fujitsu FR81 7.36 DIV1 (Main Process of Division)

CM71-00105-1E FUJITSU MICROELECTRONICS LIMITED 175
FR81 Family CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.36
7.36 DIV1 (Main Process of Division)
This is a step division instruction used for unsigned division.
●Assembler Format
DIV1 Ri
●Operation
{MDH, MDL} <<= 1 /* 1 bit left shift */
if (D1==1) {
MDH + Ri → temp
}
else {
MDH - Ri → temp
}
if ({D0 ^ D1 ^ C} == 0) {
temp → MDH
1 → MDL[0]
}
●Flag Change
N, V: Unchanged.
Z: Set when the result of step division is zero, cleared otherwise. Set according to remainder of division
results, not according to quotient.
C: Set when the operation result of step division involves a carry operation, cleared otherwise.
●Classification
Multiply/Divide Instruction
●Execution Cycles
1 cycle
NZVC
-C-C