5.6.3.2 Ultra DMA data burst timing requirements

Table 5.16 Ultra DMA data burst timing requirements (1 of 2)

NAME

MODE 0

MODE 1

MODE 2

MODE 3

MODE 4

COMMENT

 

(in ns)

(in ns)

(in ns)

(in ns)

(in ns)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

(see Notes 1 and 2)

 

 

 

 

 

 

 

 

 

 

 

 

t2CYCTYP

240

 

160

 

120

 

90

 

60

 

Typical sustained average two cycle

 

 

 

 

 

 

 

 

 

 

 

time

 

 

 

 

 

 

 

 

 

 

 

 

tCYC

112

 

73

 

54

 

39

 

25

 

Cycle time allowing for asymmetry

 

 

 

 

 

 

 

 

 

 

 

and clock variations (from STROBE

 

 

 

 

 

 

 

 

 

 

 

edge to STROBE edge)

 

 

 

 

 

 

 

 

 

 

 

 

t2CYC

230

 

154

 

115

 

86

 

57

 

Two cycle time allowing for clock

 

 

 

 

 

 

 

 

 

 

 

variations (from rising edge to next

 

 

 

 

 

 

 

 

 

 

 

rising edge or from falling edge to

 

 

 

 

 

 

 

 

 

 

 

next falling edge of STROBE)

 

 

 

 

 

 

 

 

 

 

 

 

tDS

15

 

10

 

7

 

7

 

5

 

Data setup time (at recipient)

 

 

 

 

 

 

 

 

 

 

 

(see Note 4)

 

 

 

 

 

 

 

 

 

 

 

 

tDH

5

 

5

 

5

 

5

 

5

 

Data hold time (at recipient)

 

 

 

 

 

 

 

 

 

 

 

(see Note 4)

 

 

 

 

 

 

 

 

 

 

 

 

tDVS

70

 

48

 

30

 

20

 

6

 

Data valid setup time at sender (from

 

 

 

 

 

 

 

 

 

 

 

data valid until STROBE edge)

 

 

 

 

 

 

 

 

 

 

 

(see Note 5)

 

 

 

 

 

 

 

 

 

 

 

 

tDVH

6

 

6

 

6

 

6

 

6

 

Data valid hold time at sender (from

 

 

 

 

 

 

 

 

 

 

 

STROBE edge until data may

 

 

 

 

 

 

 

 

 

 

 

become invalid) (see Note 5)

 

 

 

 

 

 

 

 

 

 

 

 

tFS

0

230

0

200

0

170

0

130

0

120

First STROBE time (for device to

 

 

 

 

 

 

 

 

 

 

 

first negate DSTROBE from STOP

 

 

 

 

 

 

 

 

 

 

 

during a data in burst)

 

 

 

 

 

 

 

 

 

 

 

 

tLI

0

150

0

150

0

150

0

100

0

100

Limited interlock time (see Note 3)

 

 

 

 

 

 

 

 

 

 

 

 

tMLI

20

 

20

 

20

 

20

 

20

 

Interlock time with minimum

 

 

 

 

 

 

 

 

 

 

 

(see Note 3)

 

 

 

 

 

 

 

 

 

 

 

 

tUI

0

 

0

 

0

 

0

 

0

 

Unlimited interlock time (see Note 3)

 

 

 

 

 

 

 

 

 

 

 

 

tAZ

 

10

 

10

 

10

 

10

 

10

Maximum time allowed for output

 

 

 

 

 

 

 

 

 

 

 

drivers to release (from asserted or

 

 

 

 

 

 

 

 

 

 

 

negated)

 

 

 

 

 

 

 

 

 

 

 

 

tZAH

20

 

20

 

20

 

20

 

20

 

Minimum delay time required for

 

 

 

 

 

 

 

 

 

 

 

output

 

 

 

 

 

 

 

 

 

 

 

 

tZAD

0

 

0

 

0

 

0

 

0

 

Drivers to assert or negate (from

 

 

 

 

 

 

 

 

 

 

 

released)

 

 

 

 

 

 

 

 

 

 

 

 

tENV

20

70

20

70

20

70

20

55

20

55

Envelope time (from DMACK- to

 

 

 

 

 

 

 

 

 

 

 

STOP and HDMARDY- during data

 

 

 

 

 

 

 

 

 

 

 

in burst initiation and from DMACK

 

 

 

 

 

 

 

 

 

 

 

to STOP during data out burst

 

 

 

 

 

 

 

 

 

 

 

initiation)

 

 

 

 

 

 

 

 

 

 

 

 

tSR

 

50

 

30

 

20

 

NA

 

NA

STROBE-to-DMARDY-time (if

 

 

 

 

 

 

 

 

 

 

 

DMARDY- is negated before this long

 

 

 

 

 

 

 

 

 

 

 

after STROBE edge, the recipient shall

 

 

 

 

 

 

 

 

 

 

 

receive no more than one additional

 

 

 

 

 

 

 

 

 

 

 

data word)

 

 

 

 

 

 

 

 

 

 

 

 

tRFS

 

75

 

70

 

60

 

60

 

60

Ready-to-final-STROBE time (no

 

 

 

 

 

 

 

 

 

 

 

STROBE edges shall be sent this

 

 

 

 

 

 

 

 

 

 

 

long after negation of DMARDY-)

 

 

 

 

 

 

 

 

 

 

 

 

tRP

160

 

125

 

100

 

100

 

100

 

Ready-to-pause time (that recipient

 

 

 

 

 

 

 

 

 

 

 

shall wait to pause after negating

 

 

 

 

 

 

 

 

 

 

 

DMARDY-)

 

 

 

 

 

 

 

 

 

 

 

 

tIORDYZ

 

20

 

20

 

20

 

20

 

20

Maximum time before releasing

 

 

 

 

 

 

 

 

 

 

 

IORDY

 

 

 

 

 

 

 

 

 

 

 

 

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Fujitsu MPE3XXXAT manual Dmardy

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