PC/104-Plus PCI Bus Signals
The following are brief descriptions of the
Address and Data
AD[31:00] — Address and Data are multiplexed. A bus transaction consists of an address cycle followed by one or more data cycles.
C/BE[3:0]# — Bus Command/Byte Enables are multiplexed. During the address cycle, the command is defined. During the Data cycle, they define the byte enables.
PAR — Parity is even on AD[31:00] and C/BE[3:0]# and is required.
Interface Control Pins
FRAME# — Frame is driven by the current master to indicate the start of a transaction and will remain active until the final data cycle.
TRDY# — Target Ready indicates the selected devices ability to complete the current data cycle of the transaction. Both IRDY# and TRDY# must be asserted to terminate a data cycle.
IRDY# — Initiator Ready indicates the master's ability to complete the current data cycle of the transaction.
STOP# — Stop indicates the current selected device is requesting the master to stop the current transaction.
DEVSEL# — Device Select is driven by the target device when its address is decoded. IDSEL[3:0] — Initialization Device Select is used as a
Error Reporting
PERR# — Parity Error is for reporting data parity errors.
SERR# — System Error is for reporting address parity errors.
Arbitration (Bus Masters Only)
REQ[3:0]# — Request indicates to the arbitrator that this device desires use of the bus. GNT[3:0]# — Grant indicates to the requesting device that access has been granted.
System
CLK — Clock provides timing for all transactions on the PCI bus.
RST# — Reset is used to bring
Interrupts
INTA# — Interrupt A is used to request Interrupts.
INTB# — Interrupt B is used to request Interrupts only for
INTC# — Interrupt C is used to request Interrupts only for
INTD# — Interrupt D is used to request Interrupts only for
50 CMX158886 cpuModule |
