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Intel 80L186EC Writedouble Code 09H, Loadaddress Code 0AH, Readpc Code 10H, Writepc Code 11H

Models: 80L188EB 80C188EC 80C188EB 80L186EB 80C186EB 80L186EC 80C186EC 80L188EC

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INTEL 186 EB/EC EVALUATION BOARD USER’S MANUAL

6.5.8WRITE_DOUBLE (Code 09H)

This command stores the RISM_DATA register in the double-word of memory pointed to by the RISM_ADDR register and increments the RISM_ADDR register (by four) to point at the next memory double-word.

6.5.9LOAD_ADDRESS (Code 0AH)

This command loads the RISM_ADDR register with the least-significant word in the RISM_DATA register.

6.5.10 READ_PC (Code 10H)

This command loads the RISM_DATA register with the CS (Code Segment) and IP (Instruction Pointer) associated with the user’s code. Most RISM implementations have to check RUN_FLAG to determine how to access the user’s PC.

6.5.11 WRITE_PC (Code 11H)

This command loads the CS (Code Segment) and the IP (Instruction Pointer) associated with the user’s code from the RISM_DATA register. The host software will invoke this command only while user code is not running.

6.5.12 START_USER (Code 12H)

This command starts execution of user code, clears the TRAP_FLAG, and sets the RUN_FLAG. The action of this command relies on its being executed as part of an ISR (Interrupt Service Routine). At the start of the ISR, the current CS:IP and FLAGS are pushed into the stack. If the user code is not running, the CS:IP and FLAGS that are pushed into the stack are associated with an idle loop that the RISM runs while it waits for an inter- rupt. The START_USER command deletes the CS:IP and FLAGS from the stack and replaces them with USER_CS, USER_IP and USER_FLAGS. When control returns from the ISR, the user’s code (rather than the idle loop) executes. The host software will not issue a GO command if the user code is already running.

6.5.13 STOP_USER (code 13H)

This command stops the execution of user code and clears the RUN_FLAG. The action of the HALT command mirrors that of the GO command. In the case of the HALT command, the user’s CS:IP and FLAGS are pushed into the stack upon entry to the ISR. The STOP_USER command saves this user information in USER_CS, USER_IP, and USER_FLAGS and replaces it with CS:IP and FLAGS values associated with the idle loop. When control returns from the ISR, the idle loop (rather than the user’s code) executes. The host software will not issue a HALT command unless the user code is running.

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Intel 80L186EC, 80L188EC Writedouble Code 09H, Loadaddress Code 0AH, Readpc Code 10H, Writepc Code 11H, Startuser Code 12H
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80L188EB, 80C188EC, 80C188EB, 80L186EB, 80C186EB specifications

The Intel 80L188EC, 80C186EC, 80L186EC, 80C186EB, and 80L186EB microprocessors represent a significant evolution in Intel's 16-bit architecture, serving various applications in embedded systems and computing during the late 1980s and early 1990s. These microprocessors are designed to offer a blend of performance, efficiency, and versatility, making them suitable for a range of environments, including industrial control, telecommunications, and personal computing.

The Intel 80L188EC is a member of the 186 family, notable for its low-power consumption and integrated support for a range of peripheral devices. It operates at clock speeds of up to 10 MHz and features a 16-bit architecture, providing a balance of processing power and energy efficiency. The 80C186EC, on the other hand, is a more advanced version, offering enhanced performance metrics with faster clock speeds and improved processing capabilities, making it ideal for applications that require more computational power.

The 80L186EC shares similarities with the 80L188EC but is enhanced further for various low-power applications, especially where battery life is crucial. With a maximum clock speed of 16 MHz, it excels in scenarios demanding energy-efficient processing without sacrificing performance.

In contrast, the 80C186EB and 80L186EB are optimized versions that bring additional features to the table. The 80C186EB operates at higher clock speeds, coupled with an extended instruction set, enabling it to handle more complex tasks and run sophisticated software. These enhancements allow it to serve well in environments that require reliable performance under load, such as data acquisition systems or advanced control systems.

The 80L186EB is tailored for specific low-power scenarios, integrating Intel's sophisticated low-power technologies without compromising on speed. Utilizing advanced process technologies, these chips benefit from reduced heat output and extended operating life, a significant advantage in embedded applications.

Overall, these microprocessors showcase Intel's commitment to innovation in 16-bit processing, marked by their varying capabilities and power profiles tailored to meet the demands of diverse applications, from industrial systems to consumer electronics. Their legacy continues to influence subsequent generations of microprocessor designs, emphasizing performance, energy efficiency, and versatile applications in computing technology. As such, the Intel 80C186 and 80L188 families play a crucial role in understanding the evolution of microprocessor technology.