Appendix B Technical Summary

I/O Address

Read Target

Write Target

Internal Unit

80h

DMA Controller

DMA controller &

DMA

 

 

LPC/PCI

 

81h-83h

DMA Controller

DMA Controller

DMA

84h-86h

DMA Controller

DMA Controller &

DMA

 

 

LPC or PCI

 

87h

DMA Controller

DMA Controller

DMA

88h

DMA Controller

DMA Controller &

DMA

 

 

LPC or PCI

 

89h-8Bh

DMA Controller

DMA Controller

DMA

8Ch-8Eh

DMA Controller

DMA Controller &

DMA

 

 

LPC or PCI

 

08Fh

DMA Controller

DMA Controller

DMA

90h-91h

DMA Controller

DMA Controller

DMA

92h

Reset Generator

Reset Generator

Processor I/F

93h-9Fh

DMA Controller

DMA Controller

DMA

A0h-A1h

Interrupt Controller

Interrupt Controller

Interrupt

A4h-A5h

Interrupt Controller

Interrupt Controller

Interrupt

A8h-A9h

Interrupt Controller

Interrupt Controller

Interrupt

ACh-ADh

Interrupt Controller

Interrupt Controller

Interrupt

B0h-B1h

Interrupt Controller

Interrupt Controller

Interrupt

B2h-B3h

Power Management

Power Management

Power Management

B4h-B5h

Interrupt Controller

Interrupt Controller

Interrupt

B8h-B9h

Interrupt Controller

Interrupt Controller

Interrupt

BCh-BDh

Interrupt Controller

Interrupt Controller

Interrupt

C0h-D1h

DMA Controller

DMA Controller

DMA

D2h-DDh

Reserved

DMA Controller

DMA

DEh-DFh

DMA Controller

DMA Controller

DMA

F0h

See Note 3

FERR# /IGNNE#/

Processor interface

 

 

Interrupt Controller

 

170h-177h

IDE Controller1

IDE Controller1

Forwarded to IDE

1F0h-1F7h

IDE Controller2

IDE Controller2

Forwarded to IDE

376h

IDE Controller1

IDE Controller1

Forwarded to IDE

3F6h

IDE Controller2

IDE Controller2

Forwarded to IDE

4D0h-4D1h

Interrupt Controller

Interrupt Controller

Interrupt

CF9h

Reset Generator

Reset Generator

Processor interface

Notes:

1.Only if IDE Standard I/O space is enabled for Primary Drive. Otherwise, the target is PCI.

2.Only if IDE Standard I/O space is enabled for Secondary Drive. Otherwise, the target is PCI.

3.If POS_DEC_EN bit is enabled, reads from F0h will not be decoded by the ICH2. If

POS_DEC_EN is not enabled, reads from F0h will forward to LPC.

PPC-7508F USERS MANUAL

Page: B-7

Page 109
Image 109
Intel PPC-7508F M1 user manual Address Read Target Write Target Internal Unit, Ferr# /Ignne#