Intel PPC-7508F M1 user manual B-8

Appendix B Technical Summary

Memory Decode Ranges From Processor Perspective :

Memory Range	Target	Dependency/Comments
0000 0000h-000D FFFFh	Main Memory	TOM registers in Host Controller
0010 0000-TOM (Top of
Memory)
000E 0000h-000F FFFFh	FWH	Bit 7 in FWH Decode Enable
		Register is set
FEC0 0000h-FEC0 0100h	I/O APIC inside ICH2
FFC0 0000h-FFC7 FFFFh	FWH	Bit 0 in FWH Decode Enable
FF80 0000h-FF87 FFFFh		Register
FFC8 0000h-FFCF FFFFh	FWH	Bit 1 in FWH Decode Enable
FF88 0000h-FF8F FFFFh		Register
FFD0 0000h-FFD7 FFFFh	FWH	Bit 2 in FWH Decode Enable
FF90 0000h-FF97 FFFFh		Register is set
FFD8 0000h-FFDF FFFFh	FWH	Bit 3 in FWH Decode Enable
FF98 0000h-FF9F FFFFh		Register is set
FFE0 0000h-FFE7 FFFFh	FWH	Bit 4 in FWH Decode Enable
FFA0 0000h-FFA7 FFFFh		Register is set
FFE8 0000h-FFEF FFFFh	FWH	Bit 5 in FWH Decode Enable
FFA8 0000h-FFAF FFFFh		Register is set
FFF0 0000h-FFF7 FFFFh	FWH	Bit 6 in FWH Decode Enable
FFB0 0000h-FFB7 FFFFh		Register is set
FFF8 0000h-FFFF FFFFh	FWH	Always Enabled.
FFB8 0000h-FFBF FFFFh		The top two 64K blocks of this
		range can be swapped as
		described in Section 6.4.1.
FF70 0000h-FF7F FFFFh	FWH	Bit 3 in FWH Decode Enable 2
FF30 0000h-FF3F FFFFh		Register is set
FF60 0000h-FF6F FFFFh	FWH	Bit 2 in FWH Decode Enable 2
FF20 0000h-FF2F FFFFh		Register is set
FF50 0000h-FF5F FFFFh	FWH	Bit 1 in FWH Decode Enable 2
FF10 0000h-FF1F FFFFh		Register is set
FF40 0000h-FF4F FFFFh	FWH	Bit 0 in FWH Decode Enable 2
FF00 0000h-FF0F FFFFh		Register is set
Anywhere in 4GB range	D110 LAN Controller	Enable via BAR in Device
		29:Function 0 (D110 LAN
		Controller)
All Other	PCI	None

Page: B-8 PPC-7508F USER′S MANUAL