Intel S875WP1-E manual Interrupts

(Note 1)

(Note 1)

Interrupts

The interrupts can be routed through the Advanced Programmable Interrupt Controller (APIC) portion of the ICH5-R component. The APIC is supported in Windows* 2000 Server and Windows XP and supports a total of twenty-four interrupts.

Table 47. Interrupts

IRQ

NMI

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

Note:

System Resource

I/O channel check

Reserved, interval timer

Reserved, keyboard buffer full

Reserved, cascade interrupt from slave PIC

COM2

COM1

LPT2 (Plug and Play option)/User available

Diskette drive

LPT1 (Note 1)

Real-time clock

Reserved for ICH5-R system management bus

User available

User available

Onboard mouse port (if present, else user available)

Reserved, math coprocessor

Primary IDE (if present, else user available)

Secondary IDE (if present, else user available)

USB UHCI controller 1 (through PIRQA)

User available (through PIRQB)

ICH5-R USB controller 3 (through PIRQC)

ICH5-R USB controller 2 (through PIRQD)

ICH5-R LAN (through PIRQE)

User available (through PIRQF)

User available (through PIRQG)

ICH5-R USB 2.0 EHCI controller/User available (through PIRQH)

1.Default, but can be changed to another IRQ.

106 Intel Server Board S875WP1-E Product Guide