Intel S875WP1-E manual Intel 875P Chipset, Intel 82875P Memory Controller Hub MCH

•Support for 128 Mb, 256 Mb, and 512 Mb memory technologies for the following memory configurations:

Up to 1.0 GB utilizing 128 Mb technology

Up to 2.0 GB utilizing 256 Mb technology

Up to 4.0 GB utilizing 512 Mb technology

Only DIMMs tested and qualified by Intel or a designated memory test vendor will be supported on the S875WP1-E server board. Note that all DIMMs are supported by design, but only fully qualified DIMMs will be supported. Mixed mode DDR DS-DIMMs (x8 and x16 on the same DIMM) is not supported. Check the Intel Customer Support website for the latest tested memory list:

http://support.intel.com/support/motherboards/server/S875WP1-E

Intel 875P Chipset

The Intel 875P chipset consists of the following devices:

•Intel 82875P Memory Controller Hub (MCH) with Accelerated Hub Architecture (AHA) bus

•Intel 82801EB I/O Controller Hub (ICH5) with AHA bus

•Intel 82802AC Firmware Hub (FWH)

The MCH is a centralized controller for the system bus, the memory bus, the AGP bus, and the Accelerated Hub Architecture interface. The ICH5-R is a centralized controller for the board’s I/O paths. The FWH provides the nonvolatile storage of the BIOS.

Intel 82875P Memory Controller Hub (MCH)

The MCH supports the data integrity features supported by the Pentium 4 processor bus, including address, request, and response parity. The 875P chipset always generates ECC data while it is driving the processor data bus, although the data bus ECC can be disabled or enabled by BIOS. It is enabled by default. The MCH controls the Intel 82547EI from the CSA interface.

The MCH provides the following:

•An integrated DDR memory controller with auto detection.

•Support for ACPI Rev 2.0 compliant power management.

•AGP 2.0 slot, also known as AGP 8x

14 Intel Server Board S875WP1-E Product Guide