address strobe) to CAS (column address strobe). The less the clock cycles, the faster the DRAM performance.
tRP
When the DRAM Timing Mode sets to [Manual], the field is adjustable. This item controls the number of cycles for Row Address Strobe (RAS) to be al- lowed to precharge. If insufficient time is allowed for the RAS to accumulate its charge before DRAM refresh, refreshing may be incomplete and DRAM may fail to retain data. This item applies only when synchronous DRAM is installed in the system.
tRAS
When the DRAM Timing Mode sets to [Manual], the field is adjustable. This set- ting determines the time RAS takes to read from and write to a memory cell.
tRTP
When the DRAM Timing Mode sets to [Manual], the field is adjustable. Time interval between a read and a precharge command.
tRFC
When the DRAM Timing Mode sets to [Manual], the field is adjustable. This set- ting determines the time RFC takes to read from and write to a memory cell.
tWR
When the DRAM Timing Mode is set to [Manual], the field is adjustable. It speci- fies the amount of delay (in clock cycles) that must elapse after the completion of a valid write operation, before an active bank can be precharged. This delay is required to guarantee that data in the write buffers can be written to the memory cells before precharge occurs.
tRRD
When the DRAM Timing Mode sets to [Manual], the field is adjustable. Speci- fies the
tWTR
When the DRAM Timing Mode is set to [Manual], the field is adjustable. This item controls the Write Data In to Read Command Delay memory timing. This constitutes the minimum number of clock cycles that must occur between the last valid write operation and the next read command to the same internal bank of the DDR device.
FSB/DRAM Ratio
This item will allow you to adjust the ratio of FSB to memory.
Adjusted DRAM Frequency (MHz)
It shows the adjusted memory frequency.
Adjust
This item allows you to adjust the
Auto Disable DRAM/PCI Frequency
When set to [Enabled], the system will remove (turn off) clocks from empty DIMM and PCI slots to minimize the electromagnetic interference (EMI).
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