4-9 Troubleshooting
POST Codes
The code displayed using the postcard is shown below.
CP | Reason |
01 | Initialize BMC |
02 | Verify Real Mode |
03 | Test BMC |
04 | Get Processor type |
06 | Initialize system hardware |
08 | Initialize chipset registers with initial POST values |
09 | Set in POST flag |
0A | Initialize Processor registers |
0B | Enable Processor cache |
0C | Initialize caches to initial POST values |
0E | Initialize I/O |
0F | Initialize the local bus IDE |
10 | Initialize Power Management |
11 | Load alternate registers with initial POST values |
12 | Restore Processor control word during warm boot |
13 | Initialize PCI Bus mastering devices |
14 | Initialize keyboard controller |
16 | BIOS ROM checksum |
17 | Initialize external cache before memory autosize |
18 | 8254 timer initialization |
1A | 8237 DMA controller initialization |
1C | Reset Programmable Interrupt Controller |
20 | Test DRAM refresh |
22 | Test 8742 Keyboard Controller |
24 | Set ES segment register to 4GB |
28 | Autosize DRAM, system BIOS stops execution here if the BIOS does not detect any |
| usable memory DIMMs |
29 | Initializes the POST Memory Manager |
2A | Clear 8 MB base RAM |
2C | Base RAM failure, BIOS stops execution here if entire memory is bad |
2E | Test the first 4MB of RAM |
2F | Initialize external cache before shadowing |
32 | Test Processor |
33 | Initializes the Phoenix Dispatch Manager |
34 | Test CMOS |
35 | RAM Initialize alternate chipset registers |
36 | Warm start shut down |
37 | Reinitialize the chipset |
38 | Shadow system BIOS ROM |
39 | Reinitialize the cache |
3A | Autosize cache |
3C | Configure advanced chipset registers |
3D | Load alternate registers with CMOS values |
41 | Check unsupported processor |
40 | Set Initial Processor speed new |
42 | Initialize interrupt vectors |