NEC uPD75P3116 PD75P3116

µ

PD75P3116

16 Data Sheet U11369EJ3V0DS

5. DIFFERENCES BETWEEN

µ

PD75P3116 AND

µ

PD753104, 753106, 753108

The

µ

PD75P3116 replaces the internal mask ROM in the

µ

PD753104, 753106, and 753108 with a one-time PROM

and features expanded ROM capacity. The

µ

PD75P3116’s Mk I mode supports the Mk I mode in the

µ

PD753104, 753106,

and 753108 and the

µ

PD75P3116’s Mk II mode supports the Mk II mode in the

µ

PD753104, 753106, and 753108.

Table 5-1 lists differences between the

µ

PD75P3116 and the

µ

PD753104, 753106, and 753108. Be sure to check the

differences between these products before using them with PROMs for debugging or prototype testing of application

systems or, later, when using them with a mask ROM for full-scale production.

For details of the CPU functions and internal hardware, refer to the User’s Manual.

Table 5-1. Differences Between

µ

PD75P3116 and

µ

PD753104, 753106, and 753108

Item

µ

PD753104

µ

PD753106

µ

PD753108

µ

PD75P3116

Program counter 12 bits 13 bits 14 bits

Program memory (bytes) Mask ROM Mask ROM Mask ROM One-time PROM

4096 6144 8192 16384

Data memory (× 4 bits) 512

Mask options Pull-up resistor for Available Not available

Port 5 (On chip/not on chip can be specified.) (Not on chip)

Split resistor for

LCD driving power supply

Wait time after Available Not available

RESET (Selectable between 217/fX and 215/fX)Note (Fixed to 215/fX)Note

Feedback resistor Available Not available

of subsystem clock (Use/not use can be selected.) (Enable)

Pin configuration Pins 5 to 8 P30 to P33

P30/MD0 to P33/MD3

Pins 10 to 13 P50 to P53 P50/D4 to P53/D7

Pins 14 to 17 P60/KR0 to P63/KR3

P60/KR0/D0 to P63/KR3/D3

Pin 21 IC VPP

Other Noise resistance and noise radiation may differ due to the different circuit sizes and mask

layouts.

Note 217/fX: 21.8 ms at 6.0 MHz operation, 31.3 ms at 4.19 MHz operation

215/fX: 5.46 ms at 6.0 MHz operation, 7.81 ms at 4.19 MHz operation

Caution There are differences in the amount of noise tolerance and noise radiation between flash memory

versions and mask ROM versions. When considering changing from a flash memory version to a mask

ROM version during the process from experimental manufacturing to mass production, make sure to

sufficiently evaluate commercial samples (CS) (not engineering samples (ES)) of the mask ROM

versions.

Contents

Main DATA SHEET PD75P3116 FEATURES FUNCTION OUTLINE PD75P3116 1. PIN CONFIGURATION (TOP VIEW) 64-pin plastic QFP (14 14): Note Always connect the VPP pin directly to VDD during normal operation. PD75P3116GC-AB8 64-pin plastic LQFP (12 12): PD75P3116GK-8A8 64-pin plastic LQFP (14 14): PD75P3116 PIN IDENTIFICATIONS PD75P3116 6 2. BLOCK DIAGRAM LCD controller/driver PD75P3116 3. PIN FUNCTIONS 3.1 Port Pins (1/2) 3.1 Port Pins (2/2) 3.2 Non-Port Pins (1/2) Page PD75P3116 3.3 Pin I/O Circuits The I/O circuits for the PD75P3116s pins are shown in abbreviated form below. (Continued) 3.4 Recommended Connection of Unused Pins Table 3-1. List of Unused Pin Connections Note When the subsystem clock is not used, select SOS.0 = 1 (on-chip feedback resistor not used). 14 4. Mk I AND Mk II MODE SELECTION FUNCTION Stack area specification Mode selection specification PD75P3116 PD75P3116 AND 5. DIFFERENCES BETWEEN 16 PD753104, 753106, 753108 6. MEMORY CONFIGURATION Figure 6-1. Program Memory Map Figure 6-2. Data Memory Map Note Memory bank 0 or 1 can be selected as the stack area. 7. INSTRUCTION SET Page Page Note Only the lower 3 bits in the B register are valid. Page Page Page Note - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 28 8. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY Page Page PD75P3116 32 9. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25C) Page Page DC Characteristics (TA = 40 to +85C, VDD = 1.8 to 5.5 V) 36 DC Characteristics (TA = 40 to +85C, VDD = 1.8 to 5.5 V) AC Characteristics (TA = 40 to +85C, VDD = 1.8 to 5.5 V) Page SBI mode (SCK...Internal clock output (master)): (TA = 40 to +85C, VDD = 1.8 to 5.5 V) AC Timing Test Points (Excluding X1, XT1 Input) Clock Timing TI0, TI1, TI2 Timing Serial Transfer Timing 3-wire serial I/O mode 2-wire serial I/O mode Serial Transfer Timing Bus release signal transfer Command signal transfer Interrupt input timing RESET input timing Data Memory Stop Mode Low Supply Voltage Data Retention Characteristics (TA = 40 to +85C) Data Retention Timing (STOP Mode Release by RESET) Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal) DC Programming Characteristics (TA = 25 5C, VDD = 6.0 0.25 V, VPP = 12.5 0.3 V, VSS = 0 V) Program Memory Write Timing Program Memory Read Timing Data output Data output t t V V VDD + 1 V 10. CHARACTERISTIC CURVES (REFERENCE VALUES) Supply current IDD (mA) Page 64-PIN PLASTIC QFP (14x14) 11. PACKAGE DRAWINGS 64-PIN PLASTIC LQFP (12x12) 64-PIN PLASTIC LQFP (14x14) 52 12. RECOMMENDED SOLDERING CONDITIONS Page 54 APPENDIX A. LIST OF PD75308B, 753108, AND 75P3116 FUNCTIONS Page 56 APPENDIX B. DEVELOPMENT TOOLS The following development tools have been provided for system development using the PROM Write Tools 58 Debugging Tools OS for IBM PCs The following operating systems for IBM PCs are supported. Page Page Page Notes on Target System Design Figure B-6. Connection Conditions of Target System (1) Figure B-7. Connection Conditions of Target System (2) Page Page Page 68 NOTES FOR CMOS DEVICES Regional Information Device availability Ordering information Product release schedule Availability of related technical literature