NEC uPD75P3116 3.1 Port Pins (2/2)

PD75P3116

8Data Sheet U11369EJ3V0DS

3.1 Port Pins (2/2)

Pin Name I/O Alternate Function 8-Bit Status I/O Circuit

Function I/O After Reset TypeNote 1

P60 I/O KR0/D0 Programmable 4-bit I/O port (Port 6) — Input <F>-A

Input and output can be specified in 1-bit units.

P61 KR1/D1 Connection of an internal pull-up resistor can be

specified by a software setting in 4-bit units.

P62 KR2/D2

P63 KR3/D3

P80 I/O S23 4-bit I/O port (Port 8) √Input H

Connection of an internal pull-up resistor can be

P81 S22 specified by a software setting in 4-bit unitsNote 2.

P82 S21

P83 S20

P90 I/O S19 Programmable 4-bit I/O port (Port 9) Input H

Connection of an internal pull-up resistor can be

P91 S18 specified by a software setting in 4-bit unitsNote 2.

P92 S17

P93 S16

Notes 1. Circuit types enclosed in angle brackets indicate Schmitt-triggered input.

2. Do not connect an internal pull-up resistor by software when these pins are used as segment signal outputs.

Contents

Main DATA SHEET PD75P3116 FEATURES FUNCTION OUTLINE PD75P3116 1. PIN CONFIGURATION (TOP VIEW) 64-pin plastic QFP (14 14): Note Always connect the VPP pin directly to VDD during normal operation. PD75P3116GC-AB8 64-pin plastic LQFP (12 12): PD75P3116GK-8A8 64-pin plastic LQFP (14 14): PD75P3116 PIN IDENTIFICATIONS PD75P3116 6 2. BLOCK DIAGRAM LCD controller/driver PD75P3116 3. PIN FUNCTIONS 3.1 Port Pins (1/2) 3.1 Port Pins (2/2) 3.2 Non-Port Pins (1/2) Page PD75P3116 3.3 Pin I/O Circuits The I/O circuits for the PD75P3116s pins are shown in abbreviated form below. (Continued) 3.4 Recommended Connection of Unused Pins Table 3-1. List of Unused Pin Connections Note When the subsystem clock is not used, select SOS.0 = 1 (on-chip feedback resistor not used). 14 4. Mk I AND Mk II MODE SELECTION FUNCTION Stack area specification Mode selection specification PD75P3116 PD75P3116 AND 5. DIFFERENCES BETWEEN 16 PD753104, 753106, 753108 6. MEMORY CONFIGURATION Figure 6-1. Program Memory Map Figure 6-2. Data Memory Map Note Memory bank 0 or 1 can be selected as the stack area. 7. INSTRUCTION SET Page Page Note Only the lower 3 bits in the B register are valid. Page Page Page Note - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 28 8. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY Page Page PD75P3116 32 9. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25C) Page Page DC Characteristics (TA = 40 to +85C, VDD = 1.8 to 5.5 V) 36 DC Characteristics (TA = 40 to +85C, VDD = 1.8 to 5.5 V) AC Characteristics (TA = 40 to +85C, VDD = 1.8 to 5.5 V) Page SBI mode (SCK...Internal clock output (master)): (TA = 40 to +85C, VDD = 1.8 to 5.5 V) AC Timing Test Points (Excluding X1, XT1 Input) Clock Timing TI0, TI1, TI2 Timing Serial Transfer Timing 3-wire serial I/O mode 2-wire serial I/O mode Serial Transfer Timing Bus release signal transfer Command signal transfer Interrupt input timing RESET input timing Data Memory Stop Mode Low Supply Voltage Data Retention Characteristics (TA = 40 to +85C) Data Retention Timing (STOP Mode Release by RESET) Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal) DC Programming Characteristics (TA = 25 5C, VDD = 6.0 0.25 V, VPP = 12.5 0.3 V, VSS = 0 V) Program Memory Write Timing Program Memory Read Timing Data output Data output t t V V VDD + 1 V 10. CHARACTERISTIC CURVES (REFERENCE VALUES) Supply current IDD (mA) Page 64-PIN PLASTIC QFP (14x14) 11. PACKAGE DRAWINGS 64-PIN PLASTIC LQFP (12x12) 64-PIN PLASTIC LQFP (14x14) 52 12. RECOMMENDED SOLDERING CONDITIONS Page 54 APPENDIX A. LIST OF PD75308B, 753108, AND 75P3116 FUNCTIONS Page 56 APPENDIX B. DEVELOPMENT TOOLS The following development tools have been provided for system development using the PROM Write Tools 58 Debugging Tools OS for IBM PCs The following operating systems for IBM PCs are supported. Page Page Page Notes on Target System Design Figure B-6. Connection Conditions of Target System (1) Figure B-7. Connection Conditions of Target System (2) Page Page Page 68 NOTES FOR CMOS DEVICES Regional Information Device availability Ordering information Product release schedule Availability of related technical literature