| 5 |
|
|
| 6 | 7 | 8 | |
|
|
|
|
|
|
|
|
|
Pin No. |
| Pin Name | I/O | Format |
| Function and Operation |
| |
62 |
| P05 | I |
|
| PLD config status input |
| |
63 |
| P04 | I |
|
| PLD config end information input |
| |
64 |
| NC |
|
|
| Not used |
| |
65 |
|
|
| O | C |
| PLD reset data output |
|
P02 |
|
| ||||||
66 |
| P01 | O | C |
| PLD chip enable output |
| |
67 |
| P00 | O | C |
| PLD chip enable output |
| |
68 |
| NC |
|
|
| Not used |
| |
69 |
| P106 | I |
|
| Band select input |
| |
70 |
| P105 | I |
|
| Ach band select input |
| |
71 |
| P104 | I |
|
| Address select input |
| |
| NC |
|
|
| Not used |
| ||
75 |
| AVSS |
|
|
| Vss |
| |
76 |
| NC |
|
|
| Not used |
| |
77 |
| VREF |
|
|
| AD translation reference voltage |
| |
78 |
| AVCC |
|
|
| Vcc |
| |
79 |
| SIN4 | I |
|
| PLD serial data input |
| |
80 |
| SOUT4 | O | C |
| PLD serial data output |
|
A
B
*PD5952A
8061
1
60
20
41
2140
Format | Meaning |
C | CMOS |
N | N ch open drain |
C
D
E
F
5 | 6 |
|
|
|
|
|
| |
|
| 123 | ||||
|
|
| 7 | 8 | ||
|