![Table 8. Block Addresses](/images/new-backgrounds/133881/13388121x1.webp)
PMC | Pm25LV512/010 |
|
|
SECTOR_ERASE, BLOCK_ERASE: Before a byte can be reprogrammed, the sector/block which contains the byte must be erased. In order to erase the Pm25LV512/010, two separate instructions must be executed. First, the device must be write enabled via the WREN instruction. Then the SECTOR ERASE or BLOCK ERASE instruction can be executed.
Table 8. Block Addresses
Block Address | Pm25LV512 Block | Pm25LV010 Block |
|
|
|
000000 to 007FFF | Block 1 | Block 1 |
|
|
|
008000 to 00FFFF | Block 2 | Block 2 |
|
|
|
010000 to 017FFF | N/A | Block 3 |
|
|
|
018000 to 01FFFF | N/A | Block 4 |
|
|
|
The BLOCK ERASE instruction erases every byte in the selected block if the block is not locked out. Block address is automatically determined if any address within the block is selected. The BLOCK ERASE instruction is internally controlled; it will automatically be timed to completion. During this time, all commands will be ignored, except RDSR instruction. The Pm25LV512/010 will automatically return to the write disable state at the completion of the BLOCK ERASE cycle.
CHIP_ERASE: As an alternative to the SECTOR and BLOCK ERASE, the CHIP ERASE instruction will erase every byte in all blocks that are not locked out. First, the device must be write enabled via the WREN instruction. Then the CHIP ERASE instruction can be executed. The CHIP ERASE instruction is internally controlled; it will automatically be timed to completion. The CHIP ERASE cycle time maximum is 100 miliseconds. During the internal erase cycle, all instructions will be ignored except RDSR. The Pm25LV512/010 will automatically return to the write disable state at the completion of the CHIP ERASE.
HOLD: The HOLD# pin is used in conjunction with the CE# pin to select the Pm25LV512/010. When the device is selected and a serial sequence is underway, HOLD# pin can be used to pause the serial communication with the master device without resetting the serial sequence. To pause, the HOLD# pin must be brought low while the SCK pin is low. To resume serial communication, the HOLD# pin is brought high while the SCK pin is low (SCK may still toggle during HOLD). Inputs to the Sl pin will be ignored while the SO pin is in the high impedance state.
HARDWARE WRITE PROTECT: The Pm25LV512/010 has a write lockout feature that can be activated by assert- ing the write protect pin (WP#). When the lockout feature is activated,
Programmable Microelectronics Corp. | 11 | Issue Date: February, 2004, Rev: 1.4 |