PMC

Pm25LV512/010

 

 

SECTOR_ERASE, BLOCK_ERASE: Before a byte can be reprogrammed, the sector/block which contains the byte must be erased. In order to erase the Pm25LV512/010, two separate instructions must be executed. First, the device must be write enabled via the WREN instruction. Then the SECTOR ERASE or BLOCK ERASE instruction can be executed.

Table 8. Block Addresses

Block Address

Pm25LV512 Block

Pm25LV010 Block

 

 

 

000000 to 007FFF

Block 1

Block 1

 

 

 

008000 to 00FFFF

Block 2

Block 2

 

 

 

010000 to 017FFF

N/A

Block 3

 

 

 

018000 to 01FFFF

N/A

Block 4

 

 

 

The BLOCK ERASE instruction erases every byte in the selected block if the block is not locked out. Block address is automatically determined if any address within the block is selected. The BLOCK ERASE instruction is internally controlled; it will automatically be timed to completion. During this time, all commands will be ignored, except RDSR instruction. The Pm25LV512/010 will automatically return to the write disable state at the completion of the BLOCK ERASE cycle.

CHIP_ERASE: As an alternative to the SECTOR and BLOCK ERASE, the CHIP ERASE instruction will erase every byte in all blocks that are not locked out. First, the device must be write enabled via the WREN instruction. Then the CHIP ERASE instruction can be executed. The CHIP ERASE instruction is internally controlled; it will automatically be timed to completion. The CHIP ERASE cycle time maximum is 100 miliseconds. During the internal erase cycle, all instructions will be ignored except RDSR. The Pm25LV512/010 will automatically return to the write disable state at the completion of the CHIP ERASE.

HOLD: The HOLD# pin is used in conjunction with the CE# pin to select the Pm25LV512/010. When the device is selected and a serial sequence is underway, HOLD# pin can be used to pause the serial communication with the master device without resetting the serial sequence. To pause, the HOLD# pin must be brought low while the SCK pin is low. To resume serial communication, the HOLD# pin is brought high while the SCK pin is low (SCK may still toggle during HOLD). Inputs to the Sl pin will be ignored while the SO pin is in the high impedance state.

HARDWARE WRITE PROTECT: The Pm25LV512/010 has a write lockout feature that can be activated by assert- ing the write protect pin (WP#). When the lockout feature is activated, locked-out sectors will be READ only. The write protect pin will allow normal read/write operations when held high. When the WP# is brought low and WPEN bit is "1", all write operations to the status register are inhibited. WP# going low while CE# is still low will interrupt a write to the status register. If the internal status register write cycle has already been initiated, WP# going low will have no effect on any write operation to the status register. The WP# pin function is blocked when the WPEN bit in the status register is "0". This will allow the user to install the Pm25LV512/010 in a system with the WP# pin tied to ground and still be able to write to the status register. All WP# pin functions are enabled when the WPEN bit is set to "1".

Programmable Microelectronics Corp.

11

Issue Date: February, 2004, Rev: 1.4

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PMC-Sierra manual Block Address Pm25LV512 Block Pm25LV010 Block
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Pm25LV512, Pm25LV010 specifications

PMC-Sierra is renowned for its high-performance semiconductor solutions, and the PM25LV010 and PM25LV512 are standout products in their lineup of serial NOR flash memory devices. These memory chips are specifically designed for a range of applications that include networking, storage, and consumer electronics, providing reliable performance and efficient data storage.

The PM25LV010 offers 1 megabit of storage capacity, while the PM25LV512 provides 512 kilobits. Both devices feature a simple serial interface that allows for quick and easy connections to various microcontrollers and digital signal processors. This makes them particularly attractive for systems that require fast access to stored data and simplified design architecture.

One of the primary features of the PM25LV010 and PM25LV512 is their high-speed read capability. With access times as low as 45 nanoseconds, these chips enable rapid data retrieval, ensuring that systems can operate effectively without bottlenecks caused by slow memory access. This is particularly crucial in applications where real-time data processing is essential, such as in communications systems or digital signal processing.

In terms of technology, both devices utilize advanced CMOS manufacturing processes that enhance their reliability and performance. They offer flexibility in programming and erasing, with full chip erase functionality and the ability to program data on a page basis. This allows for efficient updates to the stored information without the need to erase large sections of memory.

Power efficiency is another critical aspect of the PM25LV010 and PM25LV512. These devices consume very little power during both active and standby modes, making them suitable for battery-operated devices and energy-sensitive applications. Their low power consumption ensures extended operation time, which is a significant advantage in portable consumer electronics.

Additionally, both chips are designed with robust security features that aid in protecting sensitive data from unauthorized access. They support a variety of locking and protection mechanisms, ensuring that critical information remains confidential.

In summary, the PMC-Sierra PM25LV010 and PM25LV512 serial NOR flash memory devices merge high-speed performance, low power consumption, and advanced security, making them excellent choices for diverse applications in the modern digital landscape. Their design and technology cater to the growing demand for efficient, reliable, and secure memory solutions in today's rapidly evolving electronic ecosystems.
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