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PMC-Sierra Pm25LV010 manual Pm25LV512/010, Connection Diagrams, Pin Descriptions

Models: Pm25LV512 Pm25LV010

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Pm25LV512/010

PMC	Pm25LV512/010

CONNECTION DIAGRAMS

C E #

SO W P #

G N D

18

27

36

45

	Vcc	C E #	1	8	Vcc

	H O L D #	S O	2	7	H O L D #
	S C K	W P #		Top View
			3	6	S C K

	SI	G N D	4	5	SI

		8-Pin SOIC		8-Contact WSON
	PIN DESCRIPTIONS

	SYMBOL	TYPE	DESCRIPTION

			Chip Enable: CE# goes low activates the device's internal circuitries for
			device operation. CE# goes high deselects the device and switches into
	CE#	INPUT	standby mode to reduce the power consumption. When the device is not
			selected, data will not be accepted via the serial input pin (Sl), and the
			serial output pin (SO) will remain in a high impedance state.

	SCK	INPUT	Serial Data Clock

	SI	INPUT	Serial Data Input

	SO	OUTPUT	Serial Data Output

	GND		Ground

	Vcc		Device Power Supply

	WP#	INPUT	Write Protect: When the WP# pin brought to low and WPEN bit is "1", all
	WP#	INPUT	write operations to the status register are inhibited.
			write operations to the status register are inhibited.

	HOLD#	INPUT	Hold: Pause serial communication with the master device without
	HOLD#	INPUT	resetting the serial sequence.
			resetting the serial sequence.

Programmable Microelectronics Corp.

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Issue Date: February, 2004, Rev: 1.4

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PMC-Sierra Pm25LV010 manual Pm25LV512/010, Connection Diagrams, Pin Descriptions

Contents

512 Kbit / 1 Mbit 3.0 Volt-only, Serial Flash Memory With 25 MHz SPI Bus Interface FEATURESPm25LV512 / Pm25LV010 GENERAL DESCRIPTIONPIN DESCRIPTIONS CONNECTION DIAGRAMSPm25LV512/010 Pm25LV512/010 PRODUCT ORDERING INFORMATIONTemperature Range Part NumberPm25LV512/010 BLOCK DIAGRAMSPI Chip Block Diagram Memory ArrayFigure 1. Bus Master and SPI Memory Devices SERIAL INTERFACE DESCRIPTIONPm25LV512/010 Pm25LV512/010 SERIAL INTERFACE DESCRIPTION CONTINUEDSPI MODES Figure 2. SPI ModesProduct Identification DEVICE OPERATIONPm25LV512/010 DataPm25LV512/010 Table 3. Status Register FormatPm25LV512/010 Table 5. Block Write Protect BitsPm25LV512 Pm25LV512/010Address Pm25LV010Pm25LV512/010 Table 8. Block AddressesPm25LV512/010 ABSOLUTE MAXIMUM RATINGSDC AND AC OPERATING RANGE Part NumberPm25LV512/010 DC CHARACTERISTICSSymbol ParameterPm25LV512/010 AC CHARACTERISTICSSymbol ParameterAC WAVEFORMS1 AC CHARACTERISTICS CONTINUEDPm25LV512/010 OUTPUT TEST LOADPm25LV512/010 AC CHARACTERISTICS CONTINUEDIssue Date February, 2004, Rev COUTRDID Timing TIMING DIAGRAMSPm25LV512/010 WREN TimingWRSR Timing Pm25LV512/010RDSR Timing READ TimingPm25LV512/010 BLOCK ERASE Timing Pm25LV512/010SECTOR ERASE Timing CHIP ERASE TimingPm25LV512/010 RELIABILITY CHARACTERISTICSPROGRAM/ERASE PERFORMANCE Pm25LV512/010 PACKAGE TYPE INFORMATION 8SIssue Date February, 2004, Rev Pm25LV512/010 PACKAGE TYPE INFORMATION CONTINUED 8QIssue Date February, 2004, Rev 3.40Date REVISION HISTORYPm25LV512/010 Revision No