![Table 5. Block Write Protect Bits](/images/new-backgrounds/133881/13388117x1.webp)
PMC |
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| Pm25LV512/010 | |
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Table 5. Block Write Protect Bits |
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| Status Register Bits |
| Pm25LV512 |
| Pm25LV010 | |||
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| Array Addresses |
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Level | BP1 | BP0 |
| Locked Out |
| Block(s) | Locked Out | Block(s) |
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0 | 0 | 0 |
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| None | None |
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1(1/4) | 0 | 1 |
| None |
| None | 018000 - 01FFFF | Block 4 |
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2(1/2) | 1 | 0 |
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| 010000 - 01FFFF | Block 3, 4 |
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3(All) | 1 | 1 |
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| All Blocks | 000000 - 01FFFF | All Blocks | |
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| (1 - 2) | (1 - 4) | |||||
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The WRSR instruction also allows the user to enable or disable the Write Protect (WP#) pin through the use of the Write Protect Enable (WPEN) bit. Hardware write protection is enabled when the WP# pin is low and the WPEN bit is "1". Hardware write protection is disabled when either the WP# pin is high or the WPEN bit is "0." When the device is hardware write protected, writes to the Status Register, including the Block Protect bits and the WPEN bit, and the
Note: When the WPEN bit is hardware write protected, it cannot be changed back to "0", as long as the WP# pin is held low.
Table 6. WPEN Operation
WPEN | WP | WEN | ProtectedBlocks | UnprotectedBlocks | Status Register |
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0 | X | 0 | Protected | Protected | Protected |
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0 | X | 1 | Protected | Writable | Writable |
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1 | Low | 0 | Protected | Protected | Protected |
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1 | Low | 1 | Protected | Writable | Protected |
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X | High | 0 | Protected | Protected | Protected |
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X | High | 1 | Protected | Writable | Writable |
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Programmable Microelectronics Corp. | 9 | Issue Date: February, 2004, Rev: 1.4 |