PMC-Sierra Pm25LV010 manual Pm25LV512/010, SPI Chip Block Diagram, Memory Array

Models: Pm25LV512 Pm25LV010

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PMC	Pm25LV512/010

SPI Chip Block Diagram
	High Voltage
	Generator
Control Logic
	Instruction Decoder
	Serial /Parallel convert Logic
Address Latch	2KBit Page Buffer	Status
& Counter		Register
D E C O D E R	Memory Array
Y -
	X - D E C O D E R

Programmable Microelectronics Corp.

Issue Date: February, 2004, Rev: 1.4

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Contents

With 25 MHz SPI Bus Interface FEATURES Pm25LV512 / Pm25LV010512 Kbit / 1 Mbit 3.0 Volt-only, Serial Flash Memory GENERAL DESCRIPTIONPm25LV512/010 CONNECTION DIAGRAMSPIN DESCRIPTIONS PRODUCT ORDERING INFORMATION Pm25LV512/010Part Number PackageBLOCK DIAGRAM SPI Chip Block DiagramPm25LV512/010 Memory ArrayPm25LV512/010 SERIAL INTERFACE DESCRIPTIONFigure 1. Bus Master and SPI Memory Devices SERIAL INTERFACE DESCRIPTION CONTINUED SPI MODESPm25LV512/010 Figure 2. SPI ModesDEVICE OPERATION Pm25LV512/010Product Identification DataPm25LV512/010 Table 3. Status Register FormatPm25LV512/010 Table 5. Block Write Protect BitsPm25LV512/010 AddressPm25LV512 Pm25LV010Pm25LV512/010 Table 8. Block AddressesABSOLUTE MAXIMUM RATINGS DC AND AC OPERATING RANGEPm25LV512/010 Part NumberDC CHARACTERISTICS SymbolPm25LV512/010 ParameterAC CHARACTERISTICS SymbolPm25LV512/010 ParameterAC CHARACTERISTICS CONTINUED Pm25LV512/010AC WAVEFORMS1 OUTPUT TEST LOADAC CHARACTERISTICS CONTINUED Issue Date February, 2004, RevPm25LV512/010 COUTTIMING DIAGRAMS Pm25LV512/010RDID Timing WREN TimingPm25LV512/010 RDSR TimingWRSR Timing READ TimingPm25LV512/010 Pm25LV512/010 SECTOR ERASE TimingBLOCK ERASE Timing CHIP ERASE TimingPROGRAM/ERASE PERFORMANCE RELIABILITY CHARACTERISTICSPm25LV512/010 Issue Date February, 2004, Rev PACKAGE TYPE INFORMATION 8SPm25LV512/010 PACKAGE TYPE INFORMATION CONTINUED 8Q Issue Date February, 2004, RevPm25LV512/010 3.40REVISION HISTORY Pm25LV512/010Date Revision No