PMC

Pm25LV512/010

 

 

WRITE ENABLE (WREN): The device will power up in the write disable state when Vcc is applied. All write instructions must therefore be preceded by the WREN instruction.

WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the WRDI instruction disables all write commands. The WRDI instruction is independent of the status of the WP# pin.

READ STATUS REGISTER (RDSR): The RDSR instruction provides access to the status register. The READY/ BUSY and write enable status of the device can be determined by the RDSR instruction. Similarly, the Block Write Protection bits indicate the extent of protection employed. These bits are set by using the WRSR instruction. During internal write cycles, all other commands will be ignored except the RDSR instruction.

Table 3. Status Register Format

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

WPEN

X

X

X

BP1

BP0

WEN

RDY

Table 4. Read Status Register Bit Definition

Bit

 

Definition

 

 

 

 

 

Bit 0 = 0 indicates the device is READY.

Bit 0 (RDY)

Bit 0 = 1 indicates the write cycle is in progress and the device is

 

 

BUSY.

 

 

 

Bit 1 (WEN)

Bit 1 = 0 indicates the device is not WRITE ENABLED.

Bit 1 = 1 indicates the device is WRITE ENABLED.

 

 

 

 

 

Bit 2

(BP0)

See Table 5.

 

 

 

Bit 3

(BP1)

See Table 5.

 

 

Bits 4-6 are 0s when device is not in an internal write cycle.

 

 

 

 

 

WPEN = 0 blocks the function of Write Protect pin (WP#).

Bit 7

(WPEN)

WPEN = 1 activates the Write Protect pin (WP#).

 

 

See Table 6 for details.

 

 

Bits 0-7 are 1s during an internal write cycle.

 

 

 

WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select one of four levels of protec- tion for the Pm25LV010. The Pm25LV010 is divided into four blocks where the top quarter (1/4), top half (1/2), or all of the memory blocks can be protected (locked out) from write. The Pm25LV512 is divided into 2 blocks where all of the memory blocks can be protected (locked out) from write. Any of the locked-out blocks will therefore be READ only. The locked-out block and the corresponding status register control bits are shown in Table 5.

The three bits, BP0, BP1, and WPEN, are nonvolatile cells that have the same properties and functions as the regular memory cells (e.g., WREN, RDSR).

Programmable Microelectronics Corp.

8

Issue Date: February, 2004, Rev: 1.4

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PMC-Sierra Pm25LV512, Pm25LV010 manual Bit Definition
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Pm25LV512, Pm25LV010 specifications

PMC-Sierra is renowned for its high-performance semiconductor solutions, and the PM25LV010 and PM25LV512 are standout products in their lineup of serial NOR flash memory devices. These memory chips are specifically designed for a range of applications that include networking, storage, and consumer electronics, providing reliable performance and efficient data storage.

The PM25LV010 offers 1 megabit of storage capacity, while the PM25LV512 provides 512 kilobits. Both devices feature a simple serial interface that allows for quick and easy connections to various microcontrollers and digital signal processors. This makes them particularly attractive for systems that require fast access to stored data and simplified design architecture.

One of the primary features of the PM25LV010 and PM25LV512 is their high-speed read capability. With access times as low as 45 nanoseconds, these chips enable rapid data retrieval, ensuring that systems can operate effectively without bottlenecks caused by slow memory access. This is particularly crucial in applications where real-time data processing is essential, such as in communications systems or digital signal processing.

In terms of technology, both devices utilize advanced CMOS manufacturing processes that enhance their reliability and performance. They offer flexibility in programming and erasing, with full chip erase functionality and the ability to program data on a page basis. This allows for efficient updates to the stored information without the need to erase large sections of memory.

Power efficiency is another critical aspect of the PM25LV010 and PM25LV512. These devices consume very little power during both active and standby modes, making them suitable for battery-operated devices and energy-sensitive applications. Their low power consumption ensures extended operation time, which is a significant advantage in portable consumer electronics.

Additionally, both chips are designed with robust security features that aid in protecting sensitive data from unauthorized access. They support a variety of locking and protection mechanisms, ensuring that critical information remains confidential.

In summary, the PMC-Sierra PM25LV010 and PM25LV512 serial NOR flash memory devices merge high-speed performance, low power consumption, and advanced security, making them excellent choices for diverse applications in the modern digital landscape. Their design and technology cater to the growing demand for efficient, reliable, and secure memory solutions in today's rapidly evolving electronic ecosystems.
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