Samsung C8274X, C8278X, F8274X, F8275X, F8278X, S3C8275X SMART OPTION , Figure 2-2. Smart Option

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESS SPACES

2-3

SMART OPTION

ROM Address: 003EH

LSBMSB .7 .6 .5 .4 .3 .2 .1 .0

ISP reset vector change enable/disable bit:

0 = OBP reset vector address

1 = Normal vector (address 0100H)

NOTES:

1. After selecting ISP reset vector address in selecting ISP protection size, don't select upper than ISP

area size.

2. When any values are written in the Smart Option area (003CH-003FH) by LDC instruction, the data of

the area may be changed but the Smart Option is not affected. The data for Smart Option should be

written in the Smart Option area (003CH-003FH) by OTP/MTP tools (SPW2 plus single

programmer, or GW-PRO2 gang programmer).

ISP reset vector address selection bit:

00 = 200H (ISP area size: 256 byte)

01 = 300H (ISP area size: 512 byte)

10 = 500H (ISP area size: 1024 byte)

11 = 900H (ISP area size: 2048 byte)

ISP protection size selection:

(note)

00 = 256 bytes

01 = 512 bytes

10 = 1024 bytes

11 = 2048 bytes

Not used

ISP protection enable/disable bit:

0 = Enable (not erasable by LDC)

1 = Disable (erasable by LDC)

ROM Address: 003FH

LSBMSB .7 .6 .5 .4 .3 .2 .1 .0

Not used LVR enable/disable bit

(criteria voltage: 2.2V):

0 = Disable LVR

1 = Enable LVR

ROM Address: 003CH

LSBMSB .7 .6 .5 .4 .3 .2 .1 .0

Not used

ROM Address: 003DH

LSBMSB .7 .6 .5 .4 .3 .2 .1 .0

Not used

These bits should be

always logic "110b".

Figure 2-2. Smart Option

Contents

Main Important Notice NOTIFICATION OF REVISIONS Page REVISION DESCRIPTIONS 1. Electrical Data 2. Condition of Operating Voltage 3. CHAPTHER 16. Embedded Flash Memory Interface 4. CHAPTHER 7. Clock Circuit Descriptions of Revision 1.4 Preface Table of Contents Part I Programming Model Chapter 1 Product Overview Chapter 2 Address Spaces Chapter 3 Addressing Modes Chapter 4 Control Registers Chapter 5 Interrupt Structure Chapter 6 Instruction Set Part II Hardware Descriptions Chapter 7 Clock Circuit Chapter 8 RESET and Power-Down Chapter 9 I/O Ports Chapter 10 Basic Timer Chapter 11 Timer 1 Chapter 12 Watch Timer Chapter 13 LCD Controller/Driver Chapter 14 Serial I/O Interface Chapter 15 Battery Level Detector Chapter 16 Embedded Flash Memory Interface Chapter 17 Electrical Data Chapter 18 Mechanical Data Chapter 19 S3F8275X/F8278X/F8274X Flash MCU Chapter 20 Development Tools Page List of Figures List of Figures List of Figures (Concluded) List of Tables List of Tables (Continued) List of Programming Tips List of Register Descriptions Page List of Instruction Descriptions 1 S3C8-SERIES MICROCONTROLLERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X MICROCONTROLLER FLASH FEATURES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X PRODUCT OVERVIEW 1-3 BLOCK DIAGRAM Figure 1-1. Block Diagram PIN ASSIGNMENT S3C8275X/F8275X S3C8278X/F8278X S3C8274X/F8274X Figure 1-2. S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Pin Assignments (64-QFP-1420F) (64-QFP-1420F) S3C8275X/F8275X S3C8278X/F8278X S3C8274X/F8274X (64-LQFP-1010) Figure 1-3. S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Pin Assignments (64-LQFP-1010) PIN DESCRIPTIONS Table 1-1. S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Pin Descriptions Pin Names Pin No. Shared Type Pin No. Shared Type Pin Description Circuit Type Pin Functions PIN CIRCUITS V Figure 1-6. Pin Circuit Type E-4 (P0, P1) Figure 1-4. Pin Circuit Type A P-Channel N-Channel Figure 1-7. Pin Circuit Type H-4 Figure 1-8. Pin Circuit Type H-8 (P2.1 P2.7, P3) PRODUCT OVERVIEW S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Figure 1-9. Pin Circuit Type H-9 (P4, P5, P6) 1-10 Figure 1-10. Pin Circuit Type H-10 (P2.0) 2 ADDRESS SPACES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 2-2 PROGRAM MEMORY (ROM) Figure 2-1. Program Memory Address Space SMART OPTION Figure 2-2. Smart Option Page REGISTER ARCHITECTURE ~ ~ ~ ~ ~ Figure 2-3. Internal Register File Organization (S3C8275X) S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESS SPACES ~ ~ 2-7 ~ ~ Figure 2-4. Internal Register File Organization (S3C8278X/C8274X) Page Page Page Page ~ ~ Page Page REGISTER ADDRESSING ADDRESS SPACES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 2-16 Figure 2-11. Register File Addressing ~ ~ ~ Page Figure 2-13. 4-Bit Working Register Addressing Figure 2-14. 4-Bit Working Register Addressing Example Page Figure 2-16. 8-Bit Working Register Addressing Example SYSTEM AND USER STACK Page 3 REGISTER ADDRESSING MODE (R) Figure 3-1. Register Addressing Figure 3-2. Working Register Addressing INDIRECT REGISTER ADDRESSING MODE (IR) INDIRECT REGISTER ADDRESSING MODE (Continued) Figure 3-4. Indirect Register Addressing to Program Memory ~~ ~~ Figure 3-5. Indirect Working Register Addressing to Register File INDIRECT REGISTER ADDRESSING MODE (Concluded) Figure 3-6. Indirect Working Register Addressing to Program or Data Memory INDEXED ADDRESSING MODE (X) ~~ ~~ + INDEXED ADDRESSING MODE (Continued) + ~~ Figure 3-8. Indexed Addressing to Program or Data Memory with Short Offset INDEXED ADDRESSING MODE (Concluded) + ~~ Figure 3-9. Indexed Addressing to Program or Data Memory DIRECT ADDRESS MODE (DA) DIRECT ADDRESS MODE (Continued) INDIRECT ADDRESS MODE (IA) RELATIVE ADDRESS MODE (RA) + IMMEDIATE MODE (IM) 4 Page Page CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 4-4 FLAGS - System Flags Register D5H Set 1 Figure 4-1. Register Description Format BLDCON BTCON CLKCON CLOCON EXTICONH EXTICONL EXTIPND FLAGS FMCON FMSECH FMSECL FMUSR IMR IPH IPL IPR IRQ LCON OSCCON P0CONH P0CONL P0PUR P1CONH P1CONL P1PUR P2CONH P2CONL P2PUR P3CONH P3CONL P3PUR P4CONH P4CONL P5CONH P5CONL P6CON PP RP0 RP1 SIOCON SPH SPL STPCON SYM TACON TBCON WTCON 5 INTERRUPT STRUCTURE S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 5-2 Figure 5-1. S3C8-Series Interrupt Types Page Page Page Page Page Page Page Page Page INTERRUPT STRUCTURE S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 5-12 Figure 5-8. Interrupt Priority Register (IPR) Page Page Page Page Page 6 Page Page Page Page Page Page Page Page Page Page Page Page ADC ADD Add AND Logical AND BAND Bit AND BCP Bit Compare BITC Bit Complement BITR BITS BOR BTJRF Bit Test, Jump Relative on False BTJRT BXOR CALL CCF CLR COM CP CPIJE CPIJNE Page DA DEC DECW DI DIV DJNZ EI ENTER EXIT IDLE INC INCW IRET JP JR Page LD LDB Page LDC/LDE LDCD/LDED LDCI/LDEI LDCPD/LDEPD LDCPI/LDEPI LDW MULT NEXT NOP OR POP POPUD POPUI PUSH PUSHUD PUSHUI RCF RET RL RLC RR RRC SB0 SB1 SBC SCF SRA SRP/SRP0/SRP1 STOP SUB SWAP TCM TM WFI XOR 7 Page S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CLOCK CIRCUIT 7-3 Figure 7-6. System Clock Circuit Diagram Page Page Page ) Page 8 SYSTEM RESET Page Page Page POWER-DOWN MODES Page 9 Page Page Figure 9-2. Port 0 High-Byte Control Register (P0CONH) Figure 9-3. Port 0 Low-Byte Control Register (P0CONL) Figure 9-4. Port 0 Pull-up Control Register (P0PUR) Figure 9-5. External Interrupt Control Register, Low Byte (EXTICONL) Figure 9-6. External Interrupt Pending Register (EXTIPND) Page Figure 9-7. Port 1 High-Byte Control Register (P1CONH) Figure 9-8. Port 1 Low-Byte Control Register (P1CONL) Figure 9-9. Port 1 Pull-up Control Register (P1PUR) Figure 9-10. External Interrupt Control Register, High Byte (EXTICONH) Figure 9-11. External Interrupt Control Register, Low Byte (EXTICONL) Figure 9-12. External Interrupt Pending Register (EXTIPND) Page Figure 9-14. Port 2 Low-byte Control Register (P2CONL) Figure 9-15. Port 2 Pull-up Control Register (P2PUR) Page Page Page Page Page Figure 9-22. Port 5 Low-Byte Control Register (P5CONL) Page 10 Page Page BASIC TIMER S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 10-4 Figure 10-2. Basic Timer Block Diagram 11 ONE 16-BIT TIMER MODE (TIMER 1) Page S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X TIMER 1 11-3 Figure 11-2. Timer 1 Block Diagram (One 16-bit Mode) TWO 8-BIT TIMERS MODE (TIMER A and B) Page Figure 11-4. Timer B Control Register (TBCON) S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X TIMER 1 11-7 Figure 11-5. Timer A Block Diagram (Two 8-bit Timers Mode) TIMER 1 S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 11-8 Figure 11-6. Timer B Block Diagram (Two 8-bit Timers Mode) 12 Page S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X WATCH TIMER 12-3 WATCH TIMER CIRCUIT DIASGRAM Figure 12-2. Watch Timer Circuit Diagram 13 LCD CIRCUIT DIAGRAM Figure 13-2. LCD Circuit Diagram Page Page S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X LCD CONTROLLER/DRIVER 13-5 LCD VOLTAGE DIVIDING RESISTOR Figure 13-5. Internal Voltage Dividing Resistor Connection Page S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X LCD CONTROLLER/DRIVER 13-7 Figure 13-7. Select/No-Select Signal in 1/2 Duty, 1/2 Bias Display Mode Figure 13-8. Select/No-Select Signal in 1/3 Duty, 1/3 Bias Display Mode LCD CONTROLLER/DRIVER S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 13-8 Figure 13-9. LCD Signals and Wave Forms Example in 1/4 Duty, 1/3 Bias Display Mode 14 Page SIO BLOCK DIAGRAM Page 15 Page 16 USER PROGRAM MODE Page Page ISPTM (ON-BOARD PROGRAMMING) SECTOR Page SECTOR ERASE Page PROGRAMMING Page READING HARD LOCK PROTECTION 17 Page Page Page Page Page Page Figure 17-4. Input Timing for RESET Figure 17-5. Serial Data Transfer Timing Page Page Page Page Page S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X MECHANICAL DATA 18-1 18 The S3C8275X/C8278X/C8274X microcontroller is currently available in a 64-pin QFP and LQFP package. 64-QFP-1420F Figure 18-1. 64-Pin QFP Package Dimensions (64-QFP-1420F) 64-LQFP-1010 Figure 18-2. 64-Pin LQFP Package Dimensions (64-LQFP-1010) 19 S3F8275X S3F8278X S3F8274X (64-QFP-1420F) Figure 19-1. S3F8275X/F8278X/F8274X Pin Assignments (64-QFP-1420F) S3F8275X S3F8278X S3F8274X (64-LQFP-1010) Figure 19-2. S3F8275X/F8278X/F8274X Pin Assignments (64-LQFP-1010) Page Page Page Page 20 Figure 20-1. SMDS Product Configuration (SMDS2+) S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X DEVELOPMENT TOOLS 20-3 TB8275/8/4 160 QFP S3E8270 EVA Chip Figure 20-2. TB8275/8/4 Target Board Configuration Page Page Page S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X DEVELOPMENT TOOLS 40-Pin DIP Connector 20-7 40-Pin DIP Connector Figure 20-3. 40-Pin Connectors (J101, J102) for TB8275/8/4 Target Board 40-Pin Connector Target Cable for 40-pin Connector J102 33 34 J101 12 Target Board