5.2.3.1

Time Base Generator

32

5.2.3.2

Automatic Gain Control

32

5.2.3.3

Asymmetry Correction Circuitry (ASC)

32

5.2.3.4 Analog Anti-Aliasing Low Pass Filter

32

5.2.3.5 Analog to Digital Converter (ADC) and FIR

32

5.3

SERVO SYSTEM

34

5.4

READ AND WRITE OPERATIONS

34

5.4.1

 

The Read Channel

34

5.4.2

 

The Write Channel

35

5.5

FIRMWARE FEATURES

35

5.5.1

 

Read Caching

35

5.5.2

 

Write Caching

36

5.5.3

 

Defect Management

37

5.5.4

 

Automatic Defect Allocation

37

5.5.5

 

Multi-burst ECC Correction

37

5.5.6

 

SMART

37

5.5.7AAM…………………………………………………………………………………………..37

CHAPTER 6 AT INTERFACE AND ATA COMMANDS

39

6.1

INTRODUCTION

39

6.2

PHYSICAL INTERFACE

39

6.2.1

Signal Conventions

39

6.2.2

Signal Summary

39

6.2.3

Signal Descriptions

40

 

6.2.3.1 CS1FX- (Drive Chip Select 0)

40

 

6.2.3.2 CS3FX- (Drive Chip Select 1)

40

 

6.2.3.3 DA0-2 (Drive Address Bus)

40

 

6.2.3.4

DASP- (Drive Active/Slave Present)

40

 

6.2.3.5 DD0-DD15 (Drive Data Bus)

40

 

6.2.3.6

DIOR- (Drive I/O Read)

40

 

6.2.3.7

DIOW- (Drive I/O Write)

40

 

6.2.3.8

DMACK- (DMA Acknowledge)

41

 

6.2.3.9

DMARQ (DMA Request)

41

 

6.2.3.10

INTRQ (Drive Interrupt)

41

 

6.2.3.11

IOCS16- (Drive 16-bit I/O)

41

 

6.2.3.12

IORDY (I/O Channel Ready)

42

 

6.2.3.13

PDIAG- (Passed Diagnostics)

42

 

6.2.3.14

RESET- (Drive Reset)

42

6.3

LOGICAL INTERFACE

46

6.3.1

General

46

 

6.3.1.1

Bit Conventions

46

 

6.3.1.2

Environment

46

6.3.2

I/O Register - Address

48

6.3.3

Control Block Register Descriptions

49

 

6.3.3.1 Alternate Status Register (3F6h)

49

 

6.3.3.2 Drive Address Register (3F7h)

49

 

6.3.3.3 Device Control Register (3F6h)

49

6.3.4

Command Block Register Descriptions

50

 

6.3.4.1

Data Register (1F0h)

50

 

6.3.4.2

Features Register (1F1h)

50

 

6.3.4.3 Sector Number Register (1F3h)

50

 

6.3.4.4

Error Register (1F1h)

50

 

6.3.4.5 Sector Count Register (1F2h)

51

 

6.3.4.6 Cylinder High Register (1F5h)

51

 

6.3.4.7 Cylinder Low Register (1F4h)

51

 

6.3.4.8

Command Register (1F7h)

51

 

6.3.4.9

Drive/Head Register (1F6h)

51

 

6.3.4.10

Status Register (1F7h)

52

6.4

AT COMMAND REGISTER DESCRIPTIONS

53

6.4.1

Check Power Mode (98h, E5h)

56

6.4.2

Download Micro Code (92h)

56

6.4.3

Execute Device Diagnostics (90h)

56

iv

 

 

SpinPoint V40 Product Manual

Page 4
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Samsung spinpoint v40, 3.5 hard disk drives manual Ervo S Ystem EAD and W Rite O Perations, Irmware F Eatures, Smart