DISK DRIVE OPERATION
SpinPoint V40 Product Manual 95
Table 6-18 Multiword DMA data transfer
Multiword DMA timing parameters Mode 0
ns Mode 1
ns Mode 2
ns Note
t0 Cycle time (min) 480 150 120 see note
tD DIOR-/DIOW- (min) 215 80 70 see note
tE DIOR- data access (max) 150 60 50
tF DIOR- data hold (min) 5 5 5
tG DIOR-/DIOW- data setup (min) 100 30 20
tH DIOW- data hold (min) 20 15 10
tI DMACK to DIOR-/DIOW- setup (min) 0 0 0
tJ DIOR-/DIOW- to DMACK hold (min) 20 5 5
tKR DIOR- negated pulse width (min) 50 50 25 see note
tKW DIOW- negated pulse width (min) 215 50 25 see note
tLR DIOR- to DMARQ delay (max) 120 40 35
tLW DIOW- to DMARQ delay (max) 40 40 35
tM CS(1:0) valid to DIOR-/DIOW- (min) 50 30 25
tN CS(1:0) hold (min) 15 10 10
tZ DMACK- to tri-state (max) 20 25 25
NOTE − t0 is the minimum total cycle time, tD is the minimum command active time, and tK (tKR or tKW, as appropriate)
is the minimum command recovery time or command inactive time. The actual cycle time equals the sum of the actual
command active time and the actual command inactive time. The three timing requirements of t0, tD, tK shall be met.
The minimum total cycle time requirement, t0, is greater than the sum of tD and tK. This means a host implementation
may lengthen either or both tD or tK to ensure that t0 is equal to the value reported in the devices IDENTIFY DEVICE
data. A device implementation shall support any legal host implementation.