Timing, Register transfers | Samsung 3.5 hard disk drives specification

DISK DRIVE OPERATION

6.7Timing

The minimum cycle time supported by the device in PIO mode 3, 4 and Multiword DMA mode 1, 2 respectively, shall always be greater than, or equal to the minimum cycle time defined by the associated mode. For example, a device supporting PIO mode 4 timing shall not report a value less than 120ns, the minimum cycle time defined for PIO mode 4 timings.

6.7.1 Register transfers

Figure 6-1defines the relationships between the interface signals for register transfers. Peripherals reporting support for PIO mode 3 or 4 shall power up in a PIO mode 0, 1, or 2.

For PIO modes 3 and above, the minimum value of t0 is specified by word 68 in the IDENTIFY DEVICE parameter list. Table 6-16 defines the minimum value that shall be placed in word 68.

IORDY will be supported when PIO modes 3 or 4 are the current mode of operation.

NOTE − Some devices implementing the PACKET Command feature set prior to this standard power up in PIO mode 3 and enable IORDY as the default.

SpinPoint V40 Product Manual

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Samsung 3.5 hard disk drives, spinpoint v40 manual Timing, Register transfers

Contents

Spinpoint SpinPoint V40 Product Manual Table of Contents Irmware F Eatures Ervo S Ystem EAD and W Rite O PerationsSmart Protocol Overview Programming RequirementsTiming Service and Repair Maintenance Precautions107 General Information Table of Figures Page Manual Organization User DefinitionScope Terminology and Conventions Commands and MessagesComputer Message Format C/S Reference Introduction Key FeaturesDescription Hardware Requirements Standards and Regulations Specifications Specification Summary Logical Configurations Physical Specifications Performance Specifications 28.71 Power Requirements SV6003H SV6014H SV8004H Environmental Specifications Mtbf POH Reliability Specifications Space Requirements Installation Mounting Unpacking InstructionsOrientation 2Mounting Dimensions in Millimeters 3Mounting-Screw Clearance Clearance DC Power Connector Cable ConnectorsAT-Bus Interface Connector Ventilation SpinPoint V40 Product Manual Jumper Block Configurations Options for Jumper Block Configuration 7DC Power Connector and AT-Bus Interface Cable Connections Drive Installation Parameter System Startup Procedure System Setup Base Casting Assembly Head / Disk Assembly HDADC Spindle Motor Assembly Disk Drive Operation Exploded Mechanical View Head Stack Assembly Disk Stack AssemblyVoice Coil Motor and Actuator Latch Assemblies Air Filtration System Drive Electronics Digital Signal Process and Interface ControllerAT Disk Controller 2SID2001 AT Controller Block Diagram Host Interface Control Block Disk Control Block Buffer Control Block SpinPoint V40 Product Manual Read/Write IC Power ManagementDisk ECC Control Block Frequency Synthesizer Automatic Gain Control Time Base GeneratorAsymmetry Correction Circuitry ASC Analog Anti-Aliasing Low Pass Filter 3Read/Write 88C5200 Read and Write Operations Servo SystemRead Channel Write Channel Firmware FeaturesRead Caching Write Caching Automatic Defect Allocation Defect ManagementMulti-burst ECC Correction Smart Blank Signal Summary Signal ConventionsPhysical Interface Signal Descriptions Dmarq DMA Request DMACK- DMA AcknowledgeIntrq Drive Interrupt IOCS16- Drive 16-bit I/O RESET- Drive Reset PDIAG- Passed DiagnosticsIordy I/O Channel Ready SD4 SD8 SD6 SD9 SD5SD3 SD2 Drive Host Drive DIR General Logical InterfaceBit Conventions Environment SpinPoint V40 Product Manual 2 I/O Register Address Command Block RegistersControl Block Registers N N N A a a Alternate Status Register 3F6h Control Block Register DescriptionsDrive Address Register 3F7h Device Control Register 3F6h Features Register 1F1h Command Block Register DescriptionsError Register 1F1h Data Register 1F0h Sector Count Register 1F2h Command Register 1F7hCylinder High Register 1F5h Cylinder Low Register 1F4h BSY Drdy DWF DSC DRQ Corr IDX ERR Status Register 1F7h At Command Register Descriptions Command Parameter Used SpinPoint V40 Product Manual Execute Device Diagnostics 90h Check Power Mode 98h, E5hDownload Micro Code 92h Format Track 50h Flush Cache E7hIdentify Device ECh Xxxx Word Content Description Capabilities Command set supported 95-128 0000h Reserved 129-159 Vendor specific 160-255 Idle Immediate 95h,E1h Idle 97h,E3hInitialize Device Parameters 91h Read Long 22hwith retry, 23h without retry Read Buffer E4h Read Multiple Command C4h Read Sectors 20hwith retry, 21hwithout retry Read Native Max Address F8h Recalibrate 1xh Read Verify Sectors 40hwith retry, 41hwithout retrySeek 7xh Mode Set Features EFh LBA InputsNormal outputs BSY Drdy DRQ ERR Description Sleep 99h, E6h Set Multiple Mode C6h Standby 96h,E2h Smart disable operation D9hSmart B0h Smart enable operations D8h Smart enable/disable attribute autosave D2hSmart execute off-line immediate D4h Byte Descriptions Smart read data D0h Off-line data collection capability Value Definition Smart read log sector D5h Smart capabilitySmart return status DAh Smart save attribution value D3h Standby Immediate 94h, E0h Standby 96h, E2hWrite Buffer E8h Write DMA CAh Write Sectors 30hwith retry, 31hwithout retry Write Multiple Command C5h SpinPoint V40 Product Manual Error Posting Reset ResponseProgramming Requirements BBK Command Error Register Status Register Sleep mode Power ConditionsStandby mode Idle mode Normal mode Protocol Overview PIO Data in Commands PIO Read Command PIO Data Out CommandsPIO Read Aborted Command PIO Write Aborted Command PIO Write CommandBSY=0 DRDY=1 BSY=1 BSY=0 DRQ=1 BSY=1 DRQ=0 Non-Data Commands DMA Data Transfer Commands BSY=0 BSY=1 Aborted DMA Command Initialize DMA Reset DMA StatusBSY=1 BSY=0 Register transfers Timing DIOR-/DIOW Write PIO data transfers PIO timing parameters Mode Addr valid See note T1 t2 DIOR-/DIOW DIOR-/DIOW Multiword DMA data transfer Multiword DMA timing parameters Mode Initiating an Ultra DMA data in burst Ultra DMA data transfer 19Ultra DMA data burst timing requirements Ultra DMA data burst timing requirements 5Sustained Ultra DMA data in burst Sustained Ultra DMA data in burst 6Host pausing an Ultra DMA data in burst Host pausing an Ultra DMA data in burst 7Device terminating an Ultra DMA data in burst 100 Device terminating an Ultra DMA data in burst 8Host terminating an Ultra DMA data in burst Host terminating an Ultra DMA data in burst 9Initiating an Ultra DMA data out burst 102 Initiating an Ultra DMA data out burst 10Sustained Ultra DMA data out burst Sustained Ultra DMA data out burst 11Device pausing an Ultra DMA data out burst 104 Device pausing an Ultra DMA data out burst 12Host terminating an Ultra DMA data out burst Host terminating an Ultra DMA data out burst 13Device terminating an Ultra DMA data out burst 106 Device terminating an Ultra DMA data out burst Service And Repair Maintenance PrecautionsGeneral Information