Sanyo EP93F manual LC72711W, CLK16 Data

Models: EP93F

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The DARC (Data Radio Channel) FM multiplex broadcast technology was developed by NHK
(Japan Broadcasting Corporation). DARC is a registered trademark of NHK Engineering Services, Inc. (NHK-ES).
A separate contract with NHK-ES is required for the manufacturer or sale of electronic equipment that uses DARC technology.
The logo shown here may be used with electronic equipment that uses DARC technology.
SANYO for this format.
All bus addresses are managed by
:CCB is SANYO's original bus format.
SANYO for this format.
All bus addresses are managed by
:CCB is SANYO's original bus format.

Mobile FM Multiplex Broadcast (DARC System) Receiver IC

LC72711W

Overview

The LC72711W is a data demodulation IC for the reception of mobile FM multiplex broadcasts in the DARC system.

The LC72711W includes a bandpass filter for the extraction of the DARC signal from the FM baseband.

This IC is optimal for worldwide FM multiplex products since it supports all of the FM multiplex frame structures (methods A, A', B, and C) in the ITU-R recommendations.

The LC72711W and LC72711LW support both parallel connection and CCB serial interface in place of the CPU interface provided by the LC72709E.

Functions

Adjustment-free SCF based 76 kHz bandpass filter

Supports all FM multiplex frame structures (methods A, A', B, and C) under CPU control

MSK delay detection circuit using a 1T delay

Error correction function using a 2T delay (in the MSK detection stage)

Digital PLL based clock regeneration circuit

Shift register type 1T and 2T delay circuits

Block and frame synchronization detection circuits

Function for setting the allowable BIC error count and synchronization protection count

Error correction using (272,190) codes

Layer 4 CRC code checking circuit

Includes the frame memory and memory control circuit required for vertical correction

7.2 MHz crystal oscillator circuit

Two power saving modes (standby and EC stop modes)

Either a CPU parallel interface (DMA) or a CCB serial interface can be used

Supply voltage: 4.5 to 5.5 V

Package: SQFP64 (10 10 mm)

The DARC (Data Radio Channel) FM multiplex broadcast technology was developed by NHK

(Japan Broadcasting Corporation). DARC is a registered trademark of NHK Engineering Services, Inc. (NHK-ES).

A separate contract with NHK-ES is required for the manufacturer or sale of electronic equipment that uses DARC technology.

The logo shown here may be used with electronic equipment that uses DARC technology.

Block Diagram

 

 

 

 

 

 

 

CLK16

DATA

BLOCK FLOCK BCK FCK

 

 

 

 

Vddd

 

 

 

 

LPF

 

 

 

 

 

 

 

 

 

Vssd

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Error

 

 

1T delay

Clock

 

 

 

Synchronization

 

Timing

 

 

 

 

 

 

 

 

 

 

correction

STNBY

 

2T delay

regeneration

 

 

 

regeneration

 

control

 

Layer 2 CRC

 

 

 

 

 

 

 

RST

7.2MHz

 

 

 

 

 

MSK

 

 

PN

 

 

 

 

XOUT

 

 

 

LPF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

decoding

 

 

 

 

 

 

 

 

correction

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Data

XIN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Vref

 

 

 

 

 

 

 

 

 

Address

MPXIN

Antialiasing

 

76kHz

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

filter

 

BPF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(SCF)

 

 

Output control (CPU interface) and

 

Memory array

Vdda

 

 

 

 

 

 

 

 

Vref

 

 

 

 

 

layer 4 CRC checking circuit

 

 

 

 

Vssa

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VREF

FLOUT

CIN

CRC4

IOCNT1 IOCNT2

DREQ DACK CS RD WR RDY

INT D0 to D15 A0/CL A1/CE

A2/DI

A3 DO SP

BUSWD

TIN

Mobile FM Multiplexultiplex BroadcastBroadcast (DARC(DARC System)System) Receiver IC

LC72711LW11LW

Overview

The LC72711LW is a data demodulation IC for the reception of mobile FM multiplex broadcasts in the DARC system.

The LC72711LW includes a bandpass filter for the extraction of the DARC signal from the FM baseband.

This IC is optimal for worldwide FM multiplex products since it supports all of the FM multiplex frame structures (methods A, A', B, and C) in the ITU-R recommendations.

The LC72711W and LC72711LW support both parallel connection and CCB serial interface in place of the CPU interface provided by the LC72709E.

Functions

Adjustment-free SCF based 76 kHz bandpass filter

Supports all FM multiplex frame structures (methods A, A', B, and C) under CPU control

MSK delay detection circuit using a 1T delay

Error correction function using a 2T delay (in the MSK detection stage)

Digital PLL based clock regeneration circuit

Shift register type 1T and 2T delay circuits

Block and frame synchronization detection circuits

Function for setting the allowable BIC error count and synchronization protection count

Error correction using (272,190) codes

Layer 4 CRC code checking circuit

Includes the frame memory and memory control circuit required for vertical correction

7.2 MHz crystal oscillator circuit

Two power saving modes (standby and EC stop modes)

Either a CPU parallel interface (DMA) or a CCB serial interface can be used

Supply voltage: 2.7 to 3.6 V

Package: SQFP64 (10 10 mm)

Block Diagram

 

 

 

 

 

 

 

CLK16

DATA

BLOCK FLOCK BCK FCK

 

 

 

 

Vddd

 

 

 

 

LPF

 

 

 

 

 

 

 

 

 

Vssd

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Error

 

 

1T delay

Clock

 

 

 

Synchronization

 

Timing

 

 

 

 

 

 

 

 

 

 

correction

STNBY

 

2T delay

regeneration

 

 

 

regeneration

 

control

 

Layer 2 CRC

 

 

 

 

 

 

 

RST

7.2MHz

 

 

 

 

 

MSK

 

 

PN

 

 

 

 

XOUT

 

 

 

LPF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

decoding

 

 

 

 

 

 

 

 

correction

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Data

XIN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

76kHz

Vref

 

 

 

 

 

 

 

 

Address

MPXIN

Antialiasing

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

filter

 

BPF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(SCF)

 

 

Output control (CPU interface) and

 

Memory array

Vdda

 

 

 

 

 

 

 

 

Vref

 

 

 

 

 

layer 4 CRC checking circuit

 

 

 

 

Vssa

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VREF

FLOUT

CIN

CRC4

IOCNT1 IOCNT2

DREQ DACK CS RD WR RDY

INT D0 to D15 A0/CL A1/CE

A2/DI

A3 DO SP

BUSWD

TIN

 

63 Car Audio

64 Car Audio

 

 

 

Page 34
Image 34
Sanyo EP93F manual LC72711W, CLK16 Data