Sanyo EP93F manual LC72151V, LC72722/M/PM22/M/PM

Car Audio Electronic Tuning PLL

Frequency Synthesizer

LC72151V

Overview

The LC72151V is a PLL frequency synthesizer IC that includes a high-speed locking circuit for FM reception. This device makes it easy to implement high-performance RDS AM/FM tuners.

RDS Signal-ProcessingProcessingSystemSystem--onon--ChipChipICIC

LC72722/M/PM22/M/PM

Overview

The LC72722, LC72722M, and LC72722PM are system-on-chip signal demodulation and processing ICs for the European Broadcasting Union (EBU) Radio Data System (RDS) and the US National Radio System Committee (NRSC) Radio Broadcast Data System (RBDS).

Functions

■High-speed programmable dividers

◆FMIN: 10 to 160 MHz pulse swallower

◆AMIN: 2 to 40 MHz pulse swallower

0.5to 10 MHz direct divider

■IF counters

◆HCTR: 0.4 to 25 MHZ for FM IF counting

◆LCTR: 10 to 500 kHz for AM IF counting

1.0to 20 103 Hz for frequency measurement

■Reference frequency

◆One of 11 frequencies can be selected (crystal element: 10.25 or 10.35 MHz)

◆1.3❋, 3.125, 5, 6.25, 9❋, 10, 12.5, 25, 30❋, and 50 kHz

❋: These frequencies cannot be used when a 10.25 crystal element is used.

■Phase comparator

◆Supports dead zone control

◆Unlocked state detection circuit

◆Deadlock clear circuit

Block Diagram

■Active low-pass filter amplifier

◆Built-in operational amplifier for FM high-speed locking circuit

◆Built-in MOS transistor for AM

■Crystal oscillator output buffer

■I/O ports: general-purpose I/O: 2 pins ◆ Input: 4 pins (maximum)

◆ Output: 3 pins (maximum)

■Serial data I/O

◆Control and communication using the CCB format ■ Operating ranges

◆Supply voltage: 4.5 to 5.5 V (VDD)

7.5to 9.5 V (AVDD)

◆Operating temperature: -40 to +85°C

■Package: SSOP30 (275 mil)

❋ :CCB is SANYO's original bus format. All bus addresses are managed by SANYO for this format.

These ICs integrate, on the same chip, bandpass filter, demodulation, synchronization, and error correction circuits as well as buffer RAM, and provide effective error correction using soft decision error correction.

Functions

■Bandpass filter: switched capacitor filter (SCF)

■Demodulation: RDS data clock regeneration and demodulated data reliability information

■Synchronization: Block synchronization detection with variable forward and backward protection conditions

■Error correction: soft decision and hard decision error correction

■Buffer RAM: 24 blocks (about 500 ms) of data and flag memory

■Data I/O: CCB interface (power on reset)

■Packages:(LC72722):DIP24S(300mil)

(LC72722M):MFP24S(300mil)

(LC72722PM):MFP24(375mil)

❋ :CCB is SANYO's original bus format. All bus addresses are managed by SANYO for this format.

Block Diagram

		XBUF
XIN	REFERENCE			PHASE DETECTOR	PDM1
	DIVIDER			CHARGE PUMP	PDM2
XOUT				PDS
					PDS
FMIN	SWALLOW COUNTER			UNLOCK	TGI1
	1/16,1/17 4bits			DETECTOR	TGI2
					TGO
AMIN	12bits PROGRAMMABLE			CHARGE PUMP	PDF
				for FAST LOCK
		DIVIDER
					AIN2
HCTR/I-3	UNIVERSAL	DATA SHIFT REGISTER		FAST LOCK UP	AOUT2
	COUNTER	LATCH		CONTROL
					AVDD
LCTR/I-4				-	AIN1
		CCB		+	AREF
		I/F			AVSS
VDD	POWER				AOUT1
	ON
VSS	RESET
	CE	DI CL DO	I/O-1I/O-2 O-3

+5V		VREF	FLOUT	CIN
Vdda				+			CLOCK
					PLL
	REFERENCE			-	(57kHz)	RECOVERY
						(1187.5Hz)
Vssa	VOLTAGE
			VREF
		57kHz
MPXIN	ANTIALIASING	BPF	SMOOTHING				DATA
		(SCF)
	FILTER		FILTER			DECODER
DO			RAM	ERROR CORRECTION
CL	CCB					SYNC/EC CONTROLLER
		(24 BLOCK DATA)		(SOFT DECISION)
DI
CE
T1		MEMORY CONTROL		CLK(4.332MHz)
	TEST					SYNC		SYNC
T2
						DETECT-1		DETECT-2
T3 to T7				OSC/DIVIDER
				XIN	XOUT

+5V

Vddd

Vssd

RDS-ID

SYNC SYR

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