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RDS Demodulator ICs
LC72723/M
Overview
The LC72723 and LC72723M are Radio Data System (RDS) demodulation and
These ICs integrate a bandpass filter, the demodulation circuit, and data buffer RAM on the same chip and allow the RDS data to be read out in slave mode operation with an externally provided clock input signal.
(Master mode operation, in which the data is output in synchronization with the internal RDS clock output, is also supported.)
Functions
■Bandpass filter: switched capacitor filter (SCF)
■RDS demodulation: 57 kHz carrier regeneration, clock regeneration, biphase and differential decoding
■Buffer RAM: 128 bits (about 100 ms)
■Data I/O: Data readout in either master or slave mode
■RDS ID detection: Supports ID reset
■Standby mode: The crystal oscillator is stopped
■Fully adjustment free
■Packages:(LC72723) : DIP16(300mil)
(LC72723M) : MFP16(225mil)
Block Diagram
+5V | VREF | FLOUT | CIN | +5V |
Vdda |
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| Vddd |
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| CLOCK |
LC72720Y/YV ![](/images/new-backgrounds/1179633/17963375xi2.webp)
![](/images/new-backgrounds/1179633/17963375xi3.webp)
![](/images/new-backgrounds/1179633/17963375xi4.webp)
Overview
The LC72720Y and LC72720YV are
Functions
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■Demodulatior: RDS data clock regeneration and demodulated data reliability information
■Synchronization: Block synchronization detection (with variable backward and forward protection conditions)
■Error correction:
■Buffer RAM: Adequate for 24 blocks of data (about 500 ms) and flag memory
■Data I/O: CCB interface (power on reset)
Features
■Error correction capability improved by
■The load on the control microprocessor can be reduced by storing decoded data in the
■Two synchronization detection circuits provide continuous and stable detection of the synchronization timing
■Data can be read out starting with the
■Fully adjustment free
■Low voltage (supply voltage: 3.0 V min) type
■Operating
■Operating temperature:
■Packages: (LC72720Y) : DIP24S(300mil)
(LC72720YV) : SSOP30(275mil)
Block Diagram
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| + | PLL | RECOVERY |
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| REFERENCE |
| - | (57kHz) |
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| VOLTAGE |
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Vssa |
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| Vssd | |
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| 57kHz |
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MPXIN | ANTIALIASING | BPF | SMOOTHING |
| DATA | RDDA |
(SCF) |
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| FILTER | FILTER |
| DECODER |
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| RDCL | |||
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| RAM | MODE |
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| (128 bit) | |
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| CLK(4.332MHz) |
| RST | |
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TEST | TEST |
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| READY | |||
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| OSC | DETECT | |
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| XIN | XOUT |
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+3.3 V |
| VREF | FLOUT | CIN |
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Vdda |
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| CLOCK | ||
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| PLL |
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| REFERENCE |
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| - | (57kHz) | RECOVERY | |||
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Vssa | VOLTAGE |
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| VREF |
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| 57kHz |
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MPXIN | ANTIALIASING | BPF | SMOOTHING |
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| DATA | ||
(SCF) |
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| FILTER | FILTER |
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| DECODER | ||||
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DO |
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| RAM | ERROR CORRECTION |
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CL | CCB |
| SYNC/EC CONTROLLER | ||||||
(24 BLOCK DATA) | (SOFT DECISION) | ||||||||
DI |
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CE |
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T1 |
| MEMORY CONTROL | CLK(4.332MHz) |
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TEST |
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| SYNC |
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T2 |
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T3 to T7 |
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| OSC/DIVIDER | |||||
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| XIN | XOUT |
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+3.3 V
Vddd
Vssd
SYNC
SYR
| 71 Car Audio | 72 Car Audio |
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