Interrupt Controller, SPC3 IRR IMR

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5.3 Interrupt Controller

The processor is informed about indication messages and various error events via the interrupt controller. Up to a total of 16 events are stored in the interrupt controller. The events are carried out on an interrupt output. The controller does not have a prioritization level and does not provide an interrupt vector (not 8259A compatible!).

The controller consists of an Interrupt Request Register (IRR), an Interrupt Mask Register (IMR), an Interrupt Register (IR), and an Interrupt Acknowledge Register (IAR).

uP uP uP SEP_INT

SPC3	S
uP	S
uP	IRR	IMR
	IRR	IMR
	R

IAR uP

INT_Pol

X/INT uP

Each event is stored in the IRR. Individual events can be suppressed via the IMR. The input in the IRR is independent of the interrupt masks. Event signals not masked out in the IMR generate the X/INT interrupt via a sum network. The user can set each event in the IRR for debugging.

Each interrupt event the processor processed must be deleted via the IAR (except for New_Prm_Data, New_DDB_Prm_Data, and New_Cfg_Data). Log ‘1’ mustbe written on the relevant bit position. If a new event and an acknowledge from the previous event are present at the IRR at the same time, the event remains stored. If the processor subsequently enables a mask, it must be ensured that no prior input is present in the IRR. For safety purposes, the position in the IRR must be deleted prior to the mask enable.

Prior to exiting the interrupt routine, the processor must set the “end of interrupt signal (E01) = 1” in the mode register. The interrupt cable is switched to inactive with this edge change. If another event must be stored, the interrupt output is not activated again until after an interrupt inactive time of at least 1 usec or 1- 2 ms. This interrupt inactive time can be set via ‘EOI_Timebase.’ This makes it possible to again come into the interrupt routine when an edge-triggered interrupt input is used.

The polarity for the interrupt output is parameterized via the INT_Pol mode bit. After the hardware reset, the output is low-active.

Address				Bit Position					Designation
Control	7	6	5	4	3	2	1	0
Register
00H	Res	Res	Res	User_	WD_DP_	Baud_	Go/Leave	MAC_	Int-Req-Reg
(Intel)				Timer_	Mode_	rate_	Data_	Reset	7..0
				Clock	Timeout	Detect	EX

Address				Bit Position					Designation
Control	15	14	13	12	11	10	9	8
Register
01H	Res	Res	DX_OUT	Diag_	New_	New_	New_	New_GC	Int-Req-Reg 7
(Intel)				Puffer_	Prm_	Cfg_	SSA_	Com	15..8
				Changed	Data	Data	Data	mand

Page 22				V1.3				SPC3 Hardware Description
2003/04							Copyright (C) Siemens AG 2003. All rights reserved.

SPC3 specifications

Siemens SPC3 is a state-of-the-art solution designed to enhance industrial automation, providing businesses with a robust platform for managing complex processes efficiently. This device epitomizes Siemens' commitment to innovation, blending cutting-edge technology with user-friendly features to deliver optimized performance across various applications.

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In summary, Siemens SPC3 represents a significant advancement in industrial automation technology. Its high-performance processing, modular adaptability, advanced communication capabilities, robust security measures, and user-friendly design make it an ideal choice for businesses striving for efficiency and innovation in their operations. The SPC3 is more than just a control device; it is a comprehensive solution that meets the evolving demands of modern industries.

Siemens manual Interrupt Controller, SPC3 IRR IMR

Models: SPC3

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SPC3