Siemens SPC3 manual Timing in the Asynchronous Intel Mode X86 Mode, ST-Vers, Parameter Min Max

SPC3 PROFIBUS Interface Center

8.5.3 Timing in the Asynchronous Intel Mode (X86 Mode) :

In 80X86 operation, SPC3 acts like memory with ready logic. The access times depend on the type of accesses.

The request for an access to SPC3 is generated from the negative edge of the read signal or the positive edge of the write signal.

SPC3 generates the Ready signal synchronously to the fed in pulse. The Ready signal is reset when the read signal or write signal is deactivated. The data bus is switched to the Tristate with XRD = 1.

No.

	AMI-Vers.		ST-Vers.
Parameter	Min	Max	Min	Max

Unit

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

Address-Setuptime to RXD ↓ or XWR ↓ XRD ↓ to Data valid (Zugriff auf RAM)

XRD ↓ to Data valid (Zugriff auf die Register)

Address (AB10..0) Holdtime after XRD or XWR − XCS ↓ Setuptime to XRD ↓ or XWR ↓ XRD-Puls-Width

Data Holdtime after XRD −

Read/Write-Inactive-Time

XCS Holdtime after XRD − or XWR − XRD/XWR ↓ to XRDY ↓ (Normal Ready) XRD/XWR ↓ to XRDY ↓ (Early Ready) XREADY-Holdtime after XRD or XWR Data Setuptime to XWR −

Data Holdtime after XWR − XWR-Pulse-Width * XRD, XWR Cycletime last XRD ￿ to XCS ￿ XCS ￿ to next XWR ￿

XWR ￿ to next XWR ￿ (XCS don’t care)

0

0

- 5

6T – 10

(115)

2

10

0

4T + 5

3T + 5

4.3

10

10

4T

6T

4T + 10

2T + 10

6T

4T+5

(88,3)

4T+18

(101,3)

6

5T+ 14

4T+ 14

12.8

0

0

-5

6T − 10

(115)

3.1

10

0

6

10

10

4T

6T

4T + 10

2T + 10

6T

3T+42.5

(105)

4T+20.2

(103,5)

10.2

5T + 16

4T + 12

22

ns ns

ns

ns ns ns

ns ns ns ns ns ns ns ns ns ns ns ns ns

Explanations:
T	=	Clock pulse cycle (48MHz)
TBD	=	to be defined
(1	=	Access to the RAM
(2	=	Access to the registers/latches
(3	=	For T = 48 MHz

SPC3 Hardware Description	V1.3	Page 49
Copyright (C) Siemens AG 2003 All rights reserved.		2003/04