Siemens SPC3 manual Reset, Timing in the Synchronous C32-Mode, ST-Vers Min Max Unit, Tbd

SPC3 PROFIBUS Interface Center

Reset:

SPC3 requires a minimum of 400 clock pulse cycles during the reset phase so that it can be reset correctly.

Reset

8.5.2 Timing in the Synchronous C32-Mode:

If SPC3 is operated at 48MHz, an 80C32 with a maximum clock pulse rate of 20MHz can be connected.

In the C32 mode, SPC3 saves the least significant addresses with the negative edge of ALE. At the same time, SPC3 expects the more significant address bits on the address bus. SPC3 generates a chipselect signal from the more significant address bits. The request for an access to SPC3 is generated from the negative edge of the read signal and from the positive edge of the write signal.

AMI-Vers.

No. Parameter Min Max

ST-Vers.
Min	Max	Unit

1

2

3

4

5

6

7

8

10

11

12

13

14

15

16

Address to ALE ↓ Setuptime

Address (AB8..15) Holdtime after XRD − or XWR − XRD ↓ to Data Out (Zugriff auf RAM)

XRD ↓ to Data Out (Zugriff auf die Register)

ALE ↓ to XRD ↓

Data Holdtime after XRD −

Data Holdtime after XWR −

Data Setuptime to XWR −

XRD − to ALE −

XRD-Pulse-Width

XWR-Pulse-Width

Address-Holdtime after ALE ↓

ALE-Puls-Width

XRD, XWR Cycletime

ALE ↓ to XWR ↓

XWR − to ALE −

10

5

20

2

10

10

10

6T - 10

4T

10

10

6T + 30

20

10

4T + 5

(88,3)

4T + 18

(101,3)

6

10		ns
5		ns
	3T+42.5	ns
	(105)
	4T+20.2	ns
	(103,5)
20		ns
3.1	10.2	ns
10		ns
10		ns
10		ns
6T − 10		ns
4T		ns
10		ns
10		ns
6T + 30		ns
20		ns
10		ns

Explanations:
T	=	Clock pulse cycle (48MHz)
TBD	=	to be defined
(1	=	Access to the RAM
(2	=	Access to the registers/latches

(3)= for T = 48MHz

SPC3 Hardware Description	V1.3	Page 47
Copyright (C) Siemens AG 2003 All rights reserved.		2003/04