Siemens SPC3 manual Imr, Iar

PROFIBUS Interface Center SPC3

The other interrupt controller registers are assigned in the bit positions, like the IRR.

Address	Register		Reset State	Assignment
02H /	Interrupt Register	Readable	All bits deleted
03H	(IR)	only
04H /	Interrupt Mask	Writable, can	All bits set	Bit =	Mask is set and the interrupt
05H	Register	be changed		1	is disabled.
	(IMR)	during			Mask is deleted and the
		operation		Bit =	interrupt is enabled.
				0
02H /	Interrupt	Writable, can	All bits deleted	Bit =	The IRR bit is deleted.
03H	Acknowledge	be changed		1	The IRR bit remains
	Register	during		Bit =	unchanged.
	(IAR)	operation		0

Figure 5.5: Additional Interrupt Registers

The ‘New_Prm_Data’, ‘New_Cfg_Data’ inputs may not eb deleted via the Interrupt Acknowledge Register. The relevant state machines delete these inputs through the user acknowledgements (for example, ‘User_Prm_Data_Okay’ etc.).

Page 24	V1.3	SPC3 Hardware Description
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